Add sdram, don't think it works though

hw/super6502_fpga/src/sim/Makefile

@@ -4,6 +4,8 @@ SIM_SRCS_LIST=sources.list
 SUPER6502_FPGA_SOURCES=$(foreach file, $(shell cat $(FPGA_SRCS_LIST)), ../../$(file))
 SIM_SOURCES=$(shell cat $(SIM_SRCS_LIST))
 
+INCLUDE=include/sdram_controller_define.vh
+
 TB_NAME=sim_top
 
 COPY_FILES=addr_map.mem init_hex.mem
@@ -14,7 +16,7 @@ waves: $(TB_NAME)
 	./$(TB_NAME) -fst
 
 $(TB_NAME): $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) $(COPY_FILES)
-	iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) -I ../../
+	iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INCLUDE) $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) -I ../../
 
 $(COPY_FILES): ../../$@
 	cp ../../$@ .

hw/super6502_fpga/src/sim/hvl/sim_top.sv

@@ -2,6 +2,8 @@
 
 module sim_top();
 
+`include "include/sdram_controller_define.vh"
+
 localparam ADDR_WIDTH = 32;
 localparam DATA_WIDTH = 32;
 
@@ -71,11 +73,48 @@ cpu_65c02 u_cpu0 (
     .SYNC   (w_cpu0_sync)
 );
 
+logic                                   w_sdr_CKE;
+logic                                   w_sdr_n_CS;
+logic                                   w_sdr_n_WE;
+logic                                   w_sdr_n_RAS;
+logic                                   w_sdr_n_CAS;
+logic   [BA_WIDTH				-1:0]   w_sdr_BA;
+logic   [ROW_WIDTH				-1:0]   w_sdr_ADDR;
+logic   [DQ_GROUP	*DQ_WIDTH	-1:0]   w_sdr_DATA;
+logic   [DQ_GROUP	*DQ_WIDTH	-1:0]   w_sdr_DATA_oe;
+logic   [DQ_GROUP				-1:0]   w_sdr_DQM;
+wire    [DQ_GROUP	*DQ_WIDTH	-1:0]   w_sdr_DQ;
+// ^ Has to be wire because of tristate/inout stuff
+
+genvar i, j;
+generate
+    for (i=0; i<DQ_GROUP*DQ_WIDTH; i=i+1)
+    begin: DQ_map
+        assign	w_sdr_DQ[i]	=	(w_sdr_DATA_oe[i]) ? w_sdr_DATA[i] : 1'bz;
+    end
+
+    for (j=0; j<DQ_GROUP; j=j+1)
+    begin : mem_inst
+        generic_sdr inst_sdr
+        (
+            .Dq(w_sdr_DQ[((j+1)*(DQ_WIDTH))-1:((j)*DQ_WIDTH)]),
+            .Addr(w_sdr_ADDR[ROW_WIDTH-1:0]),
+            .Ba(w_sdr_BA[BA_WIDTH-1:0]),
+            .Clk(~clk_200),
+            .Cke(w_sdr_CKE),
+            .Cs_n(w_sdr_n_CS),
+            .Ras_n(w_sdr_n_RAS),
+            .Cas_n(w_sdr_n_CAS),
+            .We_n(w_sdr_n_WE),
+            .Dqm(w_sdr_DQM[j])
+        );
+    end
+endgenerate
 
 super6502_fpga u_dut (
     .i_sysclk               (clk_100),
     .i_sdrclk               (clk_200),
-    .i_tACclk               (clk_200),
+    .i_tACclk               (~clk_200),
     .clk_cpu                (clk_cpu),
 
     .button_reset           (button_reset),
@@ -87,7 +126,20 @@ super6502_fpga u_dut (
     .o_cpu0_rdy             (w_cpu0_rdy),
     .o_cpu0_irqb            (w_cpu0_irqb),
     .i_cpu0_rwb             (~w_cpu0_we),
-    .i_cpu0_sync            (w_cpu0_sync)
+    .i_cpu0_sync            (w_cpu0_sync),
+
+    .o_sdr_CKE              (w_sdr_CKE),
+    .o_sdr_n_CS             (w_sdr_n_CS),
+    .o_sdr_n_WE             (w_sdr_n_WE),
+    .o_sdr_n_RAS            (w_sdr_n_RAS),
+    .o_sdr_n_CAS            (w_sdr_n_CAS),
+    .o_sdr_BA               (w_sdr_BA),
+    .o_sdr_ADDR             (w_sdr_ADDR),
+    .i_sdr_DATA             (w_sdr_DQ),
+    .o_sdr_DATA             (w_sdr_DATA),
+    .o_sdr_DATA_oe          (w_sdr_DATA_oe),
+    .o_sdr_DQM              (w_sdr_DQM)
+
 );
 
 initial begin

hw/super6502_fpga/src/sim/include/sdram_controller_define.vh

@@ -0,0 +1,80 @@
+// =============================================================================
+// Generated by efx_ipmgr
+// Version: 2023.1.150
+// IP Version: 5.0
+// =============================================================================
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+
+localparam fSYS_MHz = 100;
+localparam fCK_MHz = 200;
+localparam tIORT_u = 2;
+localparam CL = 3;
+localparam BL = 1;
+localparam DDIO_TYPE = "SOFT";
+localparam DQ_WIDTH = 8;
+localparam DQ_GROUP = 2;
+localparam BA_WIDTH = 2;
+localparam ROW_WIDTH = 13;
+localparam COL_WIDTH = 9;
+localparam tPWRUP = 200000;
+localparam tRAS = 44;
+localparam tRAS_MAX = 120000;
+localparam tRC = 66;
+localparam tRCD = 20;
+localparam tREF = 64000000;
+localparam tRFC = 66;
+localparam tRP = 20;
+localparam tWR = 2;
+localparam tMRD = 2;
+localparam SDRAM_MODE = "AXI4";
+localparam DATA_RATE = 2;
+localparam AXI_AWADDR_WIDTH = 24;
+localparam AXI_WDATA_WIDTH = 32;
+localparam AXI_ARADDR_WIDTH = 24;
+localparam AXI_RDATA_WIDTH = 32;
+localparam AXI_AWID_WIDTH = 4;
+localparam AXI_AWUSER_WIDTH = 2;
+localparam AXI_WUSER_WIDTH = 2;
+localparam AXI_BID_WIDTH = 4;
+localparam AXI_BUSER_WIDTH = 2;
+localparam AXI_ARID_WIDTH = 4;
+localparam AXI_ARUSER_WIDTH = 3;
+localparam AXI_RUSER_WIDTH = 3;

hw/super6502_fpga/src/sim/sources.list

@@ -1,3 +1,4 @@
 hvl/sim_top.sv
 sub/verilog-6502/ALU.v
-sub/verilog-6502/cpu_65c02.v
+sub/verilog-6502/cpu_65c02.v
+sub/sim_sdram/generic_sdr.v