Add sdram, don't think it works though

hw/super6502_fpga/src/sim/sources.list

@@ -1,3 +1,4 @@
 hvl/sim_top.sv
 sub/verilog-6502/ALU.v
-sub/verilog-6502/cpu_65c02.v
+sub/verilog-6502/cpu_65c02.v
+sub/sim_sdram/generic_sdr.v