Add sdram, don't think it works though

hw/super6502_fpga/addr_map.mem

@@ -2,4 +2,6 @@
 00000000 
 000001ff
 0000ff00
-0000ffff
+0000ffff
+00000200
+0000efff

hw/super6502_fpga/ip/sdram_controller/sdram_controller_define.vh

@@ -0,0 +1,80 @@
+// =============================================================================
+// Generated by efx_ipmgr
+// Version: 2023.1.150
+// IP Version: 5.0
+// =============================================================================
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+
+localparam fSYS_MHz = 100;
+localparam fCK_MHz = 200;
+localparam tIORT_u = 2;
+localparam CL = 3;
+localparam BL = 1;
+localparam DDIO_TYPE = "SOFT";
+localparam DQ_WIDTH = 8;
+localparam DQ_GROUP = 2;
+localparam BA_WIDTH = 2;
+localparam ROW_WIDTH = 13;
+localparam COL_WIDTH = 9;
+localparam tPWRUP = 200000;
+localparam tRAS = 44;
+localparam tRAS_MAX = 120000;
+localparam tRC = 66;
+localparam tRCD = 20;
+localparam tREF = 64000000;
+localparam tRFC = 66;
+localparam tRP = 20;
+localparam tWR = 2;
+localparam tMRD = 2;
+localparam SDRAM_MODE = "AXI4";
+localparam DATA_RATE = 2;
+localparam AXI_AWADDR_WIDTH = 24;
+localparam AXI_WDATA_WIDTH = 32;
+localparam AXI_ARADDR_WIDTH = 24;
+localparam AXI_RDATA_WIDTH = 32;
+localparam AXI_AWID_WIDTH = 4;
+localparam AXI_AWUSER_WIDTH = 2;
+localparam AXI_WUSER_WIDTH = 2;
+localparam AXI_BID_WIDTH = 4;
+localparam AXI_BUSER_WIDTH = 2;
+localparam AXI_ARID_WIDTH = 4;
+localparam AXI_ARUSER_WIDTH = 3;
+localparam AXI_RUSER_WIDTH = 3;

hw/super6502_fpga/ip/sdram_controller/sdram_controller_tmpl.v

@@ -0,0 +1,127 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+
+sdram_controller u_sdram_controller(
+.i_aresetn ( i_aresetn ),
+.i_AXI4_AWADDR ( i_AXI4_AWADDR ),
+.i_sysclk ( i_sysclk ),
+.i_sdrclk ( i_sdrclk ),
+.i_tACclk ( i_tACclk ),
+.i_pll_locked ( i_pll_locked ),
+.o_dbg_ref_req ( o_dbg_ref_req ),
+.o_dbg_wr_ack ( o_dbg_wr_ack ),
+.o_dbg_rd_ack ( o_dbg_rd_ack ),
+.o_dbg_n_CS ( o_dbg_n_CS ),
+.o_dbg_n_RAS ( o_dbg_n_RAS ),
+.o_dbg_n_CAS ( o_dbg_n_CAS ),
+.o_dbg_n_WE ( o_dbg_n_WE ),
+.o_dbg_BA ( o_dbg_BA ),
+.o_dbg_ADDR ( o_dbg_ADDR ),
+.o_dbg_DATA_out ( o_dbg_DATA_out ),
+.o_dbg_DATA_in ( o_dbg_DATA_in ),
+.o_pll_reset ( o_pll_reset ),
+.o_AXI4_AWREADY ( o_AXI4_AWREADY ),
+.i_AXI4_AWVALID ( i_AXI4_AWVALID ),
+.o_AXI4_WREADY ( o_AXI4_WREADY ),
+.i_AXI4_WDATA ( i_AXI4_WDATA ),
+.i_AXI4_WSTRB ( i_AXI4_WSTRB ),
+.i_AXI4_WLAST ( i_AXI4_WLAST ),
+.i_AXI4_WVALID ( i_AXI4_WVALID ),
+.o_AXI4_BVALID ( o_AXI4_BVALID ),
+.i_AXI4_BREADY ( i_AXI4_BREADY ),
+.o_AXI4_ARREADY ( o_AXI4_ARREADY ),
+.i_AXI4_ARADDR ( i_AXI4_ARADDR ),
+.i_AXI4_RREADY ( i_AXI4_RREADY ),
+.o_AXI4_RDATA ( o_AXI4_RDATA ),
+.o_AXI4_RLAST ( o_AXI4_RLAST ),
+.o_AXI4_RVALID ( o_AXI4_RVALID ),
+.i_AXI4_AWID ( i_AXI4_AWID ),
+.i_AXI4_AWSIZE ( i_AXI4_AWSIZE ),
+.i_AXI4_ARVALID ( i_AXI4_ARVALID ),
+.i_AXI4_ARID ( i_AXI4_ARID ),
+.i_AXI4_ARLEN ( i_AXI4_ARLEN ),
+.i_AXI4_ARSIZE ( i_AXI4_ARSIZE ),
+.i_AXI4_ARBURST ( i_AXI4_ARBURST ),
+.i_AXI4_AWLEN ( i_AXI4_AWLEN ),
+.o_AXI4_RID ( o_AXI4_RID ),
+.o_dbg_we ( o_dbg_we ),
+.o_dbg_last ( o_dbg_last ),
+.o_dbg_addr ( o_dbg_addr ),
+.o_dbg_din ( o_dbg_din ),
+.o_axi4_wrstate ( o_axi4_wrstate ),
+.o_fifo_wr ( o_fifo_wr ),
+.o_fifo_full ( o_fifo_full ),
+.o_fifo_empty ( o_fifo_empty ),
+.o_dbg_fifo_waddr ( o_dbg_fifo_waddr ),
+.o_dbg_fifo_re ( o_dbg_fifo_re ),
+.o_dbg_fifo_raddr ( o_dbg_fifo_raddr ),
+.o_dbg_fifo_we ( o_dbg_fifo_we ),
+.o_dbg_axi4_wlast ( o_dbg_axi4_wlast ),
+.o_shift_cnt ( o_shift_cnt ),
+.o_re_lock ( o_re_lock ),
+.o_axi4_rastate ( o_axi4_rastate ),
+.o_axi4_nwr ( o_axi4_nwr ),
+.o_axi4_arlen ( o_axi4_arlen ),
+.o_axi4_rdstate ( o_axi4_rdstate ),
+.o_sdr_rd_valid ( o_sdr_rd_valid ),
+.o_sdr_dout ( o_sdr_dout ),
+.o_dbg_re ( o_dbg_re ),
+.o_AXI4_BID ( o_AXI4_BID ),
+.i_addr ( i_addr ),
+.i_din ( i_din ),
+.i_dm ( i_dm ),
+.o_dout ( o_dout ),
+.o_sdr_state ( o_sdr_state ),
+.o_sdr_init_done ( o_sdr_init_done ),
+.o_wr_ack ( o_wr_ack ),
+.o_rd_ack ( o_rd_ack ),
+.o_ref_req ( o_ref_req ),
+.o_rd_valid ( o_rd_valid ),
+.o_sdr_CKE ( o_sdr_CKE ),
+.o_sdr_n_CS ( o_sdr_n_CS ),
+.o_sdr_n_RAS ( o_sdr_n_RAS ),
+.o_sdr_n_CAS ( o_sdr_n_CAS ),
+.o_sdr_n_WE ( o_sdr_n_WE ),
+.o_sdr_BA ( o_sdr_BA ),
+.o_sdr_ADDR ( o_sdr_ADDR ),
+.o_sdr_DATA ( o_sdr_DATA ),
+.o_sdr_DATA_oe ( o_sdr_DATA_oe ),
+.i_sdr_DATA ( i_sdr_DATA ),
+.o_sdr_DQM ( o_sdr_DQM )
+);

hw/super6502_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd

@@ -0,0 +1,220 @@
+--------------------------------------------------------------------------------
+-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved.              
+--
+-- This   document  contains  proprietary information  which   is        
+-- protected by  copyright. All rights  are reserved.  This notice       
+-- refers to original work by Efinix, Inc. which may be derivitive       
+-- of other work distributed under license of the authors.  In the       
+-- case of derivative work, nothing in this notice overrides the         
+-- original author's license agreement.  Where applicable, the           
+-- original license agreement is included in it's original               
+-- unmodified form immediately below this header.                        
+--                                                                       
+-- WARRANTY DISCLAIMER.                                                  
+--     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+--     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+--     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+--     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+--     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+--     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+--     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+--                                                                       
+-- LIMITATION OF LIABILITY.                                              
+--     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+--     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+--     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+--     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+--     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+--     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+--     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+--     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+--     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+--     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+--     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+--     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+--     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+--     APPLY TO LICENSEE.                                                
+--
+--------------------------------------------------------------------------------
+------------- Begin Cut here for COMPONENT Declaration ------
+COMPONENT sdram_controller is
+PORT (
+i_aresetn : in std_logic;
+i_AXI4_AWADDR : in std_logic_vector(23 downto 0);
+i_sysclk : in std_logic;
+i_sdrclk : in std_logic;
+i_tACclk : in std_logic;
+i_pll_locked : in std_logic;
+o_dbg_ref_req : out std_logic;
+o_dbg_wr_ack : out std_logic;
+o_dbg_rd_ack : out std_logic;
+o_dbg_n_CS : out std_logic_vector(1 downto 0);
+o_dbg_n_RAS : out std_logic_vector(1 downto 0);
+o_dbg_n_CAS : out std_logic_vector(1 downto 0);
+o_dbg_n_WE : out std_logic_vector(1 downto 0);
+o_dbg_BA : out std_logic_vector(3 downto 0);
+o_dbg_ADDR : out std_logic_vector(25 downto 0);
+o_dbg_DATA_out : out std_logic_vector(31 downto 0);
+o_dbg_DATA_in : out std_logic_vector(31 downto 0);
+o_pll_reset : out std_logic;
+o_AXI4_AWREADY : out std_logic;
+i_AXI4_AWVALID : in std_logic;
+o_AXI4_WREADY : out std_logic;
+i_AXI4_WDATA : in std_logic_vector(31 downto 0);
+i_AXI4_WSTRB : in std_logic_vector(3 downto 0);
+i_AXI4_WLAST : in std_logic;
+i_AXI4_WVALID : in std_logic;
+o_AXI4_BVALID : out std_logic;
+i_AXI4_BREADY : in std_logic;
+o_AXI4_ARREADY : out std_logic;
+i_AXI4_ARADDR : in std_logic_vector(23 downto 0);
+i_AXI4_RREADY : in std_logic;
+o_AXI4_RDATA : out std_logic_vector(31 downto 0);
+o_AXI4_RLAST : out std_logic;
+o_AXI4_RVALID : out std_logic;
+i_AXI4_AWID : in std_logic_vector(3 downto 0);
+i_AXI4_AWSIZE : in std_logic_vector(2 downto 0);
+i_AXI4_ARVALID : in std_logic;
+i_AXI4_ARID : in std_logic_vector(3 downto 0);
+i_AXI4_ARLEN : in std_logic_vector(7 downto 0);
+i_AXI4_ARSIZE : in std_logic_vector(2 downto 0);
+i_AXI4_ARBURST : in std_logic_vector(1 downto 0);
+i_AXI4_AWLEN : in std_logic_vector(7 downto 0);
+o_AXI4_RID : out std_logic_vector(3 downto 0);
+o_dbg_we : out std_logic;
+o_dbg_last : out std_logic;
+o_dbg_addr : out std_logic_vector(23 downto 0);
+o_dbg_din : out std_logic_vector(31 downto 0);
+o_axi4_wrstate : out std_logic_vector(1 downto 0);
+o_fifo_wr : out std_logic;
+o_fifo_full : out std_logic;
+o_fifo_empty : out std_logic;
+o_dbg_fifo_waddr : out std_logic_vector(7 downto 0);
+o_dbg_fifo_re : out std_logic;
+o_dbg_fifo_raddr : out std_logic_vector(7 downto 0);
+o_dbg_fifo_we : out std_logic;
+o_dbg_axi4_wlast : out std_logic;
+o_shift_cnt : out std_logic_vector(6 downto 0);
+o_re_lock : out std_logic;
+o_axi4_rastate : out std_logic_vector(1 downto 0);
+o_axi4_nwr : out std_logic;
+o_axi4_arlen : out std_logic_vector(7 downto 0);
+o_axi4_rdstate : out std_logic_vector(1 downto 0);
+o_sdr_rd_valid : out std_logic;
+o_sdr_dout : out std_logic_vector(36 downto 0);
+o_dbg_re : out std_logic;
+o_AXI4_BID : out std_logic_vector(3 downto 0);
+i_addr : in std_logic_vector(23 downto 0);
+i_din : in std_logic_vector(31 downto 0);
+i_dm : in std_logic_vector(3 downto 0);
+o_dout : out std_logic_vector(31 downto 0);
+o_sdr_state : out std_logic_vector(3 downto 0);
+o_sdr_init_done : out std_logic;
+o_wr_ack : out std_logic;
+o_rd_ack : out std_logic;
+o_ref_req : out std_logic;
+o_rd_valid : out std_logic;
+o_sdr_CKE : out std_logic_vector(1 downto 0);
+o_sdr_n_CS : out std_logic_vector(1 downto 0);
+o_sdr_n_RAS : out std_logic_vector(1 downto 0);
+o_sdr_n_CAS : out std_logic_vector(1 downto 0);
+o_sdr_n_WE : out std_logic_vector(1 downto 0);
+o_sdr_BA : out std_logic_vector(3 downto 0);
+o_sdr_ADDR : out std_logic_vector(25 downto 0);
+o_sdr_DATA : out std_logic_vector(31 downto 0);
+o_sdr_DATA_oe : out std_logic_vector(31 downto 0);
+i_sdr_DATA : in std_logic_vector(31 downto 0);
+o_sdr_DQM : out std_logic_vector(3 downto 0));
+END COMPONENT;
+---------------------- End COMPONENT Declaration ------------
+
+------------- Begin Cut here for INSTANTIATION Template -----
+u_sdram_controller : sdram_controller
+PORT MAP (
+i_aresetn => i_aresetn,
+i_AXI4_AWADDR => i_AXI4_AWADDR,
+i_sysclk => i_sysclk,
+i_sdrclk => i_sdrclk,
+i_tACclk => i_tACclk,
+i_pll_locked => i_pll_locked,
+o_dbg_ref_req => o_dbg_ref_req,
+o_dbg_wr_ack => o_dbg_wr_ack,
+o_dbg_rd_ack => o_dbg_rd_ack,
+o_dbg_n_CS => o_dbg_n_CS,
+o_dbg_n_RAS => o_dbg_n_RAS,
+o_dbg_n_CAS => o_dbg_n_CAS,
+o_dbg_n_WE => o_dbg_n_WE,
+o_dbg_BA => o_dbg_BA,
+o_dbg_ADDR => o_dbg_ADDR,
+o_dbg_DATA_out => o_dbg_DATA_out,
+o_dbg_DATA_in => o_dbg_DATA_in,
+o_pll_reset => o_pll_reset,
+o_AXI4_AWREADY => o_AXI4_AWREADY,
+i_AXI4_AWVALID => i_AXI4_AWVALID,
+o_AXI4_WREADY => o_AXI4_WREADY,
+i_AXI4_WDATA => i_AXI4_WDATA,
+i_AXI4_WSTRB => i_AXI4_WSTRB,
+i_AXI4_WLAST => i_AXI4_WLAST,
+i_AXI4_WVALID => i_AXI4_WVALID,
+o_AXI4_BVALID => o_AXI4_BVALID,
+i_AXI4_BREADY => i_AXI4_BREADY,
+o_AXI4_ARREADY => o_AXI4_ARREADY,
+i_AXI4_ARADDR => i_AXI4_ARADDR,
+i_AXI4_RREADY => i_AXI4_RREADY,
+o_AXI4_RDATA => o_AXI4_RDATA,
+o_AXI4_RLAST => o_AXI4_RLAST,
+o_AXI4_RVALID => o_AXI4_RVALID,
+i_AXI4_AWID => i_AXI4_AWID,
+i_AXI4_AWSIZE => i_AXI4_AWSIZE,
+i_AXI4_ARVALID => i_AXI4_ARVALID,
+i_AXI4_ARID => i_AXI4_ARID,
+i_AXI4_ARLEN => i_AXI4_ARLEN,
+i_AXI4_ARSIZE => i_AXI4_ARSIZE,
+i_AXI4_ARBURST => i_AXI4_ARBURST,
+i_AXI4_AWLEN => i_AXI4_AWLEN,
+o_AXI4_RID => o_AXI4_RID,
+o_dbg_we => o_dbg_we,
+o_dbg_last => o_dbg_last,
+o_dbg_addr => o_dbg_addr,
+o_dbg_din => o_dbg_din,
+o_axi4_wrstate => o_axi4_wrstate,
+o_fifo_wr => o_fifo_wr,
+o_fifo_full => o_fifo_full,
+o_fifo_empty => o_fifo_empty,
+o_dbg_fifo_waddr => o_dbg_fifo_waddr,
+o_dbg_fifo_re => o_dbg_fifo_re,
+o_dbg_fifo_raddr => o_dbg_fifo_raddr,
+o_dbg_fifo_we => o_dbg_fifo_we,
+o_dbg_axi4_wlast => o_dbg_axi4_wlast,
+o_shift_cnt => o_shift_cnt,
+o_re_lock => o_re_lock,
+o_axi4_rastate => o_axi4_rastate,
+o_axi4_nwr => o_axi4_nwr,
+o_axi4_arlen => o_axi4_arlen,
+o_axi4_rdstate => o_axi4_rdstate,
+o_sdr_rd_valid => o_sdr_rd_valid,
+o_sdr_dout => o_sdr_dout,
+o_dbg_re => o_dbg_re,
+o_AXI4_BID => o_AXI4_BID,
+i_addr => i_addr,
+i_din => i_din,
+i_dm => i_dm,
+o_dout => o_dout,
+o_sdr_state => o_sdr_state,
+o_sdr_init_done => o_sdr_init_done,
+o_wr_ack => o_wr_ack,
+o_rd_ack => o_rd_ack,
+o_ref_req => o_ref_req,
+o_rd_valid => o_rd_valid,
+o_sdr_CKE => o_sdr_CKE,
+o_sdr_n_CS => o_sdr_n_CS,
+o_sdr_n_RAS => o_sdr_n_RAS,
+o_sdr_n_CAS => o_sdr_n_CAS,
+o_sdr_n_WE => o_sdr_n_WE,
+o_sdr_BA => o_sdr_BA,
+o_sdr_ADDR => o_sdr_ADDR,
+o_sdr_DATA => o_sdr_DATA,
+o_sdr_DATA_oe => o_sdr_DATA_oe,
+i_sdr_DATA => i_sdr_DATA,
+o_sdr_DQM => o_sdr_DQM);
+------------------------ End INSTANTIATION Template ---------

hw/super6502_fpga/ip/sdram_controller/settings.json

@@ -0,0 +1,44 @@
+{
+    "args": [
+        "-o",
+        "sdram_controller",
+        "--base_path",
+        "/home/byron/Projects/super6502/hw/super6502_fpga/ip",
+        "--vlnv",
+        {
+            "vendor": "efinixinc.com",
+            "library": "memory_controller",
+            "name": "efx_sdram_controller",
+            "version": "5.0"
+        }
+    ],
+    "conf": {
+        "fCK_MHz": "200",
+        "tIORT_u": "2",
+        "CL": "3",
+        "DDIO_TYPE": "\"SOFT\"",
+        "DQ_GROUP": "2",
+        "ROW_WIDTH": "13",
+        "COL_WIDTH": "9",
+        "tPWRUP": "200000",
+        "tRAS": "44",
+        "tRAS_MAX": "120000",
+        "tRC": "66",
+        "tRCD": "20",
+        "tREF": "64000000",
+        "tRFC": "66",
+        "tRP": "20",
+        "SDRAM_MODE": "\"AXI4\"",
+        "DATA_RATE": "2"
+    },
+    "output": {
+        "external_source_source": [
+            "/home/byron/Projects/super6502/hw/super6502_fpga/ip/sdram_controller/sdram_controller_tmpl.v",
+            "/home/byron/Projects/super6502/hw/super6502_fpga/ip/sdram_controller/sdram_controller.v",
+            "/home/byron/Projects/super6502/hw/super6502_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd",
+            "/home/byron/Projects/super6502/hw/super6502_fpga/ip/sdram_controller/sdram_controller_define.vh"
+        ]
+    },
+    "sw_version": "2023.1.150",
+    "generated_date": "2024-03-04T01:51:33.450281"
+}

hw/super6502_fpga/sources.list

@@ -11,4 +11,4 @@ src/sub/rtl-common/src/rtl/axi4_lite_rom.sv
 src/sub/rtl-common/src/rtl/ff_cdc.sv
 src/sub/rtl-common/src/rtl/shallow_async_fifo.sv
 src/sub/rtl-common/src/rtl/sync_fifo.sv
-
+ip/sdram_controller/sdram_controller.v

hw/super6502_fpga/src/rtl/super_6502_fpga.sv

@@ -12,6 +12,19 @@ module super6502_fpga(
     input                       i_pll_locked,
     output  logic               o_pll_reset,
 
+    output  logic               o_sdr_CKE,
+    output  logic               o_sdr_n_CS,
+    output  logic               o_sdr_n_WE,
+    output  logic               o_sdr_n_RAS,
+    output  logic               o_sdr_n_CAS,
+    output  logic   [1:0]       o_sdr_BA,
+    output  logic   [12:0]      o_sdr_ADDR,
+    input   logic   [15:0]      i_sdr_DATA,
+    output  logic   [15:0]      o_sdr_DATA,
+    output  logic   [15:0]      o_sdr_DATA_oe,
+    output  logic   [1:0]       o_sdr_DQM,
+
+
     input           [7:0]       i_cpu0_data_from_cpu,
     input                       i_cpu0_sync,
     input                       i_cpu0_rwb,
@@ -38,10 +51,21 @@ assign o_clk_phi2 = clk_cpu;
 
 assign o_cpu0_data_oe = {8{i_cpu0_rwb}};
 
+logic vio0_reset;
+assign vio0_reset = '1;
 
 logic master_reset;
+logic sdram_ready;
+logic [3:0] w_sdr_state;
+
+logic pre_reset;
+
+assign pre_reset = button_reset & vio0_reset;
+
+assign sdram_ready = |w_sdr_state;
+
+assign master_reset = pre_reset & sdram_ready;
 
-assign master_reset = button_reset;
 
 logic                       cpu0_AWVALID;
 logic                       cpu0_AWREADY;
@@ -98,6 +122,24 @@ logic                       rom_rready;
 logic [DATA_WIDTH-1:0]      rom_rdata;
 logic [1:0]                 rom_rresp;
 
+logic                       sdram_AWVALID;
+logic                       sdram_AWREADY;
+logic  [ADDR_WIDTH-1:0]     sdram_AWADDR;
+logic                       sdram_WVALID;
+logic                       sdram_WREADY;
+logic  [DATA_WIDTH-1:0]     sdram_WDATA;
+logic  [DATA_WIDTH/8-1:0]   sdram_WSTRB;
+logic                       sdram_BVALID;
+logic                       sdram_BREADY;
+logic  [1:0]                sdram_BRESP;
+logic                       sdram_ARVALID;
+logic                       sdram_ARREADY;
+logic  [ADDR_WIDTH-1:0]     sdram_ARADDR;
+logic                       sdram_RVALID;
+logic                       sdram_RREADY;
+logic  [DATA_WIDTH-1:0]     sdram_RDATA;
+logic  [1:0]                sdram_RRESP;
+
 
 cpu_wrapper u_cpu_wrapper_0(
     .i_clk_cpu  (clk_cpu),
@@ -145,7 +187,7 @@ cpu_wrapper u_cpu_wrapper_0(
 
 axi_crossbar #(
     .N_INITIATORS(1),
-    .N_TARGETS(2)
+    .N_TARGETS(3)
 ) u_crossbar (
     .clk(i_sysclk),
     .rst(~master_reset),
@@ -168,23 +210,24 @@ axi_crossbar #(
     .ini_bvalid     ({cpu0_BVALID   }),
     .ini_bready     ({cpu0_BREADY   }),
 
-    .tgt_araddr     ({ram_araddr,   rom_araddr      }),
+    .tgt_araddr     ({ram_araddr,   rom_araddr,     sdram_ARADDR    }),
-    .tgt_arvalid    ({ram_arvalid,  rom_arvalid     }),
+    .tgt_arvalid    ({ram_arvalid,  rom_arvalid,    sdram_ARVALID   }),
-    .tgt_arready    ({ram_arready,  rom_arready     }),
+    .tgt_arready    ({ram_arready,  rom_arready,    sdram_ARREADY   }),
-    .tgt_rdata      ({ram_rdata,    rom_rdata       }),
+    .tgt_rdata      ({ram_rdata,    rom_rdata,      sdram_RDATA     }),
-    .tgt_rresp      ({ram_rresp,    rom_rresp       }),
+    .tgt_rresp      ({ram_rresp,    rom_rresp,      sdram_RRESP     }),
-    .tgt_rvalid     ({ram_rvalid,   rom_rvalid      }),
+    .tgt_rvalid     ({ram_rvalid,   rom_rvalid,     sdram_RVALID    }),
-    .tgt_rready     ({ram_rready,   rom_rready      }),
+    .tgt_rready     ({ram_rready,   rom_rready,     sdram_RREADY    }),
-    .tgt_awaddr     ({ram_awaddr,   rom_awaddr      }),
+    .tgt_awaddr     ({ram_awaddr,   rom_awaddr,     sdram_AWADDR    }),
-    .tgt_awvalid    ({ram_awvalid,  rom_awvalid     }),
+    .tgt_awvalid    ({ram_awvalid,  rom_awvalid,    sdram_AWVALID   }),
-    .tgt_awready    ({ram_awready,  rom_awready     }),
+    .tgt_awready    ({ram_awready,  rom_awready,    sdram_AWREADY   }),
-    .tgt_wdata      ({ram_wdata,    rom_wdata       }),
+    .tgt_wdata      ({ram_wdata,    rom_wdata,      sdram_WDATA     }),
-    .tgt_wvalid     ({ram_wvalid,   rom_wvalid      }),
+    .tgt_wvalid     ({ram_wvalid,   rom_wvalid,     sdram_WVALID    }),
-    .tgt_wready     ({ram_wready,   rom_wready      }),
+    .tgt_wready     ({ram_wready,   rom_wready,     sdram_WREADY    }),
-    .tgt_wstrb      ({ram_wstrb,    rom_wstrb       }),
+    .tgt_wstrb      ({ram_wstrb,    rom_wstrb,      sdram_WSTRB     }),
-    .tgt_bresp      ({ram_bresp,    rom_bresp       }),
+    .tgt_bresp      ({ram_bresp,    rom_bresp,      sdram_BRESP     }),
-    .tgt_bvalid     ({ram_bvalid,   rom_bvalid      }),
+    .tgt_bvalid     ({ram_bvalid,   rom_bvalid,     sdram_BVALID    }),
-    .tgt_bready     ({ram_bready,   rom_bready      })
+    .tgt_bready     ({ram_bready,   rom_bready,     sdram_BREADY    })
+
 );
 
 axi4_lite_rom #(
@@ -252,6 +295,79 @@ axi4_lite_ram #(
     .i_WSTRB(ram_wstrb)
 );
 
+logic [1:0] w_sdr_CKE;
+logic [1:0] w_sdr_n_CS;
+logic [1:0] w_sdr_n_RAS;
+logic [1:0] w_sdr_n_CAS;
+logic [1:0] w_sdr_n_WE;
+logic [3:0] w_sdr_BA;
+logic [25:0] w_sdr_ADDR;
+logic [31:0] w_sdr_DATA;
+logic [31:0] w_sdr_DATA_oe;
+logic [3:0] w_sdr_DQM;
+
+assign o_sdr_CKE = w_sdr_CKE[0];    //Using SOFT ddio, ignore second cycle
+assign o_sdr_n_CS = w_sdr_n_CS[0];
+assign o_sdr_n_RAS = w_sdr_n_RAS[0];
+assign o_sdr_n_CAS = w_sdr_n_CAS[0];
+assign o_sdr_n_WE = w_sdr_n_WE[0];
+assign o_sdr_BA = w_sdr_BA[0+:2];
+assign o_sdr_ADDR = w_sdr_ADDR[0+:13];
+assign o_sdr_DATA = w_sdr_DATA[0+:16];
+assign o_sdr_DATA_oe = w_sdr_DATA_oe[0+:16];
+assign o_sdr_DQM = w_sdr_DQM[0+:2];
+
+sdram_controller u_sdram_controller(
+    .i_aresetn          (pre_reset),
+    .i_sysclk           (i_sysclk),
+    .i_sdrclk           (i_sdrclk),
+    .i_tACclk           (i_tACclk),
+    .o_pll_reset        (),
+    .i_pll_locked       ('1),
+
+    .o_sdr_state        (w_sdr_state),
+
+    .i_AXI4_AWVALID     (sdram_AWVALID),
+    .o_AXI4_AWREADY     (sdram_AWREADY),
+    .i_AXI4_AWADDR      (sdram_AWADDR[23:0]),
+    .i_AXI4_WVALID      (sdram_WVALID),
+    .o_AXI4_WREADY      (sdram_WREADY),
+    .i_AXI4_WDATA       (sdram_WDATA),
+    .i_AXI4_WSTRB       (sdram_WSTRB),
+    .o_AXI4_BVALID      (sdram_BVALID),
+    .i_AXI4_BREADY      (sdram_BREADY),
+    .i_AXI4_ARVALID     (sdram_ARVALID),
+    .o_AXI4_ARREADY     (sdram_ARREADY),
+    .i_AXI4_ARADDR      (sdram_ARADDR[23:0]),
+    .o_AXI4_RVALID      (sdram_RVALID),
+    .i_AXI4_RREADY      (sdram_RREADY),
+    .o_AXI4_RDATA       (sdram_RDATA),
+
+    .i_AXI4_WLAST       (sdram_WVALID),
+    .o_AXI4_RLAST       (),
+    .i_AXI4_AWID        ('0),
+    .i_AXI4_AWSIZE      ('0),
+    .i_AXI4_ARID        ('0),
+    .i_AXI4_ARLEN       ('0),
+    .i_AXI4_ARSIZE      ('0),
+    .i_AXI4_ARBURST     ('0),
+    .i_AXI4_AWLEN       ('0),
+    .o_AXI4_RID         (),
+    .o_AXI4_BID         (),
+
+    .o_sdr_CKE          (w_sdr_CKE),
+    .o_sdr_n_CS         (w_sdr_n_CS),
+    .o_sdr_n_RAS        (w_sdr_n_RAS),
+    .o_sdr_n_CAS        (w_sdr_n_CAS),
+    .o_sdr_n_WE         (w_sdr_n_WE),
+    .o_sdr_BA           (w_sdr_BA),
+    .o_sdr_ADDR         (w_sdr_ADDR),
+    .o_sdr_DATA         (w_sdr_DATA),
+    .o_sdr_DATA_oe      (w_sdr_DATA_oe),
+    .i_sdr_DATA         ({{16'b0}, {i_sdr_DATA}}),
+    .o_sdr_DQM          (w_sdr_DQM)
+);
+
 
 
 endmodule

hw/super6502_fpga/src/sim/Makefile

@@ -4,6 +4,8 @@ SIM_SRCS_LIST=sources.list
 SUPER6502_FPGA_SOURCES=$(foreach file, $(shell cat $(FPGA_SRCS_LIST)), ../../$(file))
 SIM_SOURCES=$(shell cat $(SIM_SRCS_LIST))
 
+INCLUDE=include/sdram_controller_define.vh
+
 TB_NAME=sim_top
 
 COPY_FILES=addr_map.mem init_hex.mem
@@ -14,7 +16,7 @@ waves: $(TB_NAME)
 	./$(TB_NAME) -fst
 
 $(TB_NAME): $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) $(COPY_FILES)
-	iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) -I ../../
+	iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INCLUDE) $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) -I ../../
 
 $(COPY_FILES): ../../$@
 	cp ../../$@ .

hw/super6502_fpga/src/sim/hvl/sim_top.sv

@@ -2,6 +2,8 @@
 
 module sim_top();
 
+`include "include/sdram_controller_define.vh"
+
 localparam ADDR_WIDTH = 32;
 localparam DATA_WIDTH = 32;
 
@@ -71,11 +73,48 @@ cpu_65c02 u_cpu0 (
     .SYNC   (w_cpu0_sync)
 );
 
+logic                                   w_sdr_CKE;
+logic                                   w_sdr_n_CS;
+logic                                   w_sdr_n_WE;
+logic                                   w_sdr_n_RAS;
+logic                                   w_sdr_n_CAS;
+logic   [BA_WIDTH				-1:0]   w_sdr_BA;
+logic   [ROW_WIDTH				-1:0]   w_sdr_ADDR;
+logic   [DQ_GROUP	*DQ_WIDTH	-1:0]   w_sdr_DATA;
+logic   [DQ_GROUP	*DQ_WIDTH	-1:0]   w_sdr_DATA_oe;
+logic   [DQ_GROUP				-1:0]   w_sdr_DQM;
+wire    [DQ_GROUP	*DQ_WIDTH	-1:0]   w_sdr_DQ;
+// ^ Has to be wire because of tristate/inout stuff
+
+genvar i, j;
+generate
+    for (i=0; i<DQ_GROUP*DQ_WIDTH; i=i+1)
+    begin: DQ_map
+        assign	w_sdr_DQ[i]	=	(w_sdr_DATA_oe[i]) ? w_sdr_DATA[i] : 1'bz;
+    end
+
+    for (j=0; j<DQ_GROUP; j=j+1)
+    begin : mem_inst
+        generic_sdr inst_sdr
+        (
+            .Dq(w_sdr_DQ[((j+1)*(DQ_WIDTH))-1:((j)*DQ_WIDTH)]),
+            .Addr(w_sdr_ADDR[ROW_WIDTH-1:0]),
+            .Ba(w_sdr_BA[BA_WIDTH-1:0]),
+            .Clk(~clk_200),
+            .Cke(w_sdr_CKE),
+            .Cs_n(w_sdr_n_CS),
+            .Ras_n(w_sdr_n_RAS),
+            .Cas_n(w_sdr_n_CAS),
+            .We_n(w_sdr_n_WE),
+            .Dqm(w_sdr_DQM[j])
+        );
+    end
+endgenerate
 
 super6502_fpga u_dut (
     .i_sysclk               (clk_100),
     .i_sdrclk               (clk_200),
-    .i_tACclk               (clk_200),
+    .i_tACclk               (~clk_200),
     .clk_cpu                (clk_cpu),
 
     .button_reset           (button_reset),
@@ -87,7 +126,20 @@ super6502_fpga u_dut (
     .o_cpu0_rdy             (w_cpu0_rdy),
     .o_cpu0_irqb            (w_cpu0_irqb),
     .i_cpu0_rwb             (~w_cpu0_we),
-    .i_cpu0_sync            (w_cpu0_sync)
+    .i_cpu0_sync            (w_cpu0_sync),
+
+    .o_sdr_CKE              (w_sdr_CKE),
+    .o_sdr_n_CS             (w_sdr_n_CS),
+    .o_sdr_n_WE             (w_sdr_n_WE),
+    .o_sdr_n_RAS            (w_sdr_n_RAS),
+    .o_sdr_n_CAS            (w_sdr_n_CAS),
+    .o_sdr_BA               (w_sdr_BA),
+    .o_sdr_ADDR             (w_sdr_ADDR),
+    .i_sdr_DATA             (w_sdr_DQ),
+    .o_sdr_DATA             (w_sdr_DATA),
+    .o_sdr_DATA_oe          (w_sdr_DATA_oe),
+    .o_sdr_DQM              (w_sdr_DQM)
+
 );
 
 initial begin

hw/super6502_fpga/src/sim/include/sdram_controller_define.vh

@@ -0,0 +1,80 @@
+// =============================================================================
+// Generated by efx_ipmgr
+// Version: 2023.1.150
+// IP Version: 5.0
+// =============================================================================
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+
+localparam fSYS_MHz = 100;
+localparam fCK_MHz = 200;
+localparam tIORT_u = 2;
+localparam CL = 3;
+localparam BL = 1;
+localparam DDIO_TYPE = "SOFT";
+localparam DQ_WIDTH = 8;
+localparam DQ_GROUP = 2;
+localparam BA_WIDTH = 2;
+localparam ROW_WIDTH = 13;
+localparam COL_WIDTH = 9;
+localparam tPWRUP = 200000;
+localparam tRAS = 44;
+localparam tRAS_MAX = 120000;
+localparam tRC = 66;
+localparam tRCD = 20;
+localparam tREF = 64000000;
+localparam tRFC = 66;
+localparam tRP = 20;
+localparam tWR = 2;
+localparam tMRD = 2;
+localparam SDRAM_MODE = "AXI4";
+localparam DATA_RATE = 2;
+localparam AXI_AWADDR_WIDTH = 24;
+localparam AXI_WDATA_WIDTH = 32;
+localparam AXI_ARADDR_WIDTH = 24;
+localparam AXI_RDATA_WIDTH = 32;
+localparam AXI_AWID_WIDTH = 4;
+localparam AXI_AWUSER_WIDTH = 2;
+localparam AXI_WUSER_WIDTH = 2;
+localparam AXI_BID_WIDTH = 4;
+localparam AXI_BUSER_WIDTH = 2;
+localparam AXI_ARID_WIDTH = 4;
+localparam AXI_ARUSER_WIDTH = 3;
+localparam AXI_RUSER_WIDTH = 3;

hw/super6502_fpga/src/sim/sources.list

@@ -1,3 +1,4 @@
 hvl/sim_top.sv
 sub/verilog-6502/ALU.v
-sub/verilog-6502/cpu_65c02.v
+sub/verilog-6502/cpu_65c02.v
+sub/sim_sdram/generic_sdr.v

hw/super6502_fpga/super6502_fpga.xml

@@ -1,4 +1,4 @@
-<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Sun Mar 03 2024 17:03:26" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Sun Mar 03 2024 18:01:28" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion" />
         <efx:device name="T20F256" />
@@ -24,7 +24,11 @@
     </efx:constraint_info>
     <efx:sim_info />
     <efx:misc_info />
-    <efx:ip_info />
+    <efx:ip_info>
+        <efx:ip instance_name="sdram_controller" path="ip/sdram_controller/settings.json">
+            <efx:ip_src_file name="sdram_controller.v" />
+        </efx:ip>
+    </efx:ip_info>
     <efx:synthesis tool_name="efx_map">
         <efx:param name="work_dir" value="work_syn" value_type="e_string" />
         <efx:param name="write_efx_verilog" value="on" value_type="e_bool" />
@@ -51,6 +55,7 @@
         <efx:param name="seq-opt-sync-only" value="0" value_type="e_option" />
         <efx:param name="mult_input_regs_packing" value="1" value_type="e_option" />
         <efx:param name="mult_output_regs_packing" value="1" value_type="e_option" />
+        <efx:param name="include" value="ip/sdram_controller" value_type="e_string" />
     </efx:synthesis>
     <efx:place_and_route tool_name="efx_pnr">
         <efx:param name="work_dir" value="work_pnr" value_type="e_string" />
@@ -81,4 +86,9 @@
         <efx:param name="cold_boot" value="off" value_type="e_bool" />
         <efx:param name="cascade" value="off" value_type="e_option" />
     </efx:bitstream_generation>
+    <efx:debugger>
+        <efx:param name="work_dir" value="work_dbg" value_type="e_string" />
+        <efx:param name="auto_instantiation" value="off" value_type="e_bool" />
+        <efx:param name="profile" value="NONE" value_type="e_string" />
+    </efx:debugger>
 </efx:project>

sw/test_code/loop_test/main.s

@@ -6,8 +6,7 @@
 .addr      _init       ; Reset vector
 .addr      _irq_int    ; IRQ/BRK vector
 
-.zeropage
+SDRAM= $200
-tmp: .res 1
 
 .code
 
@@ -17,8 +16,8 @@ _irq_int:
 _init:
         lda #$00
 @start:
-        sta tmp
+        sta SDRAM
-        cmp tmp
+        cmp SDRAM
         bne @end
         ina
         bra @start