Add memory

hw/efinix_fpga/simulation/include/super6502_sdram_controller_define.vh

@@ -1,7 +1,52 @@
+// =============================================================================
+// Generated by efx_ipmgr
+// Version: 2023.1.150
+// IP Version: 5.0
+// =============================================================================
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
 
 localparam fSYS_MHz = 100;
 localparam fCK_MHz = 200;
 localparam tIORT_u = 2;
+localparam CL = 3;
 localparam BL = 1;
 localparam DDIO_TYPE = "SOFT";
 localparam DQ_WIDTH = 8;
@@ -11,13 +56,25 @@ localparam ROW_WIDTH  = 13;
 localparam COL_WIDTH = 9;
 localparam tPWRUP = 200000;
 localparam tRAS = 44;
+localparam tRAS_MAX = 120000;
 localparam tRC = 66;
 localparam tRCD = 20;
 localparam tREF = 64000000;
+localparam tRFC = 66;
+localparam tRP = 20;
 localparam tWR = 2;
 localparam tMRD = 2;
-localparam tRFC  = 66;
+localparam SDRAM_MODE = "Native";
-localparam tRAS_MAX = 120000;
 localparam DATA_RATE = 2;
-localparam tRP = 20;
+localparam AXI_AWADDR_WIDTH = 24;
-localparam CL = 3;
+localparam AXI_WDATA_WIDTH = 32;
+localparam AXI_ARADDR_WIDTH = 24;
+localparam AXI_RDATA_WIDTH = 32;
+localparam AXI_AWID_WIDTH = 4;
+localparam AXI_AWUSER_WIDTH = 2;
+localparam AXI_WUSER_WIDTH = 2;
+localparam AXI_BID_WIDTH = 4;
+localparam AXI_BUSER_WIDTH = 2;
+localparam AXI_ARID_WIDTH = 4;
+localparam AXI_ARUSER_WIDTH = 3;
+localparam AXI_RUSER_WIDTH = 3;

hw/efinix_fpga/simulation/src/sim_top.sv

@@ -2,11 +2,13 @@
 
 module sim_top();
 
+`include "include/super6502_sdram_controller_define.vh"
+
 logic r_sysclk, r_sdrclk, r_clk_50, r_clk_2;
 
 // clk_100
 initial begin
-	r_sysclk <= '0;
+	r_sysclk <= '1;
 	forever begin
 		#5 r_sysclk <= ~r_sysclk;
 	end
@@ -54,7 +56,7 @@ end
 logic w_cpu_reset;
 logic [15:0] w_cpu_addr;
 logic [7:0] w_cpu_data_from_cpu, w_cpu_data_from_dut;
-logic cpu_rwb;
+logic w_cpu_we;
 logic w_cpu_phi2;
 
 //TODO: this
@@ -66,8 +68,8 @@ cpu_65c02 u_cpu(
 	.IRQ('0),
 	.NMI('0),
 	.DI_s1(w_cpu_data_from_dut),
-	// .DO(w_cpu_data_from_cpu),
+	.DO(w_cpu_data_from_cpu),
-	.WE(cpu_rwb)
+	.WE(w_cpu_we)
 );
 
 
@@ -91,10 +93,60 @@ super6502 u_dut(
 	.cpu_resb(w_cpu_reset),
 	.cpu_addr(w_cpu_addr),
 	.cpu_data_out(w_cpu_data_from_dut),
-	// .cpu_data_in(w_cpu_data_from_cpu),
+	.cpu_data_in(w_cpu_data_from_cpu),
-	.cpu_rwb(~cpu_rwb),
+	.cpu_rwb(~w_cpu_we),
-	.cpu_phi2(w_cpu_phi2)
+	.cpu_phi2(w_cpu_phi2),
+
+	.o_sdr_CKE(w_sdr_CKE),
+	.o_sdr_n_CS(w_sdr_n_CS),
+	.o_sdr_n_WE(w_sdr_n_WE),
+	.o_sdr_n_RAS(w_sdr_n_RAS),
+	.o_sdr_n_CAS(w_sdr_n_CAS),
+	.o_sdr_BA(w_sdr_BA),
+	.o_sdr_ADDR(w_sdr_ADDR),
+	.i_sdr_DATA(w_sdr_DQ),
+	.o_sdr_DATA(w_sdr_DATA),
+	.o_sdr_DATA_oe(w_sdr_DATA_oe),
+    .o_sdr_DQM(w_sdr_DQM)
 );
 
+wire	w_sdr_CKE;
+wire	w_sdr_n_CS;
+wire	w_sdr_n_WE;
+wire	w_sdr_n_RAS;
+wire	w_sdr_n_CAS;
+wire	[BA_WIDTH				-1:0]w_sdr_BA;
+wire	[ROW_WIDTH				-1:0]w_sdr_ADDR;
+wire	[DQ_GROUP	*DQ_WIDTH	-1:0]w_sdr_DATA;
+wire	[DQ_GROUP	*DQ_WIDTH	-1:0]w_sdr_DATA_oe;
+wire	[DQ_GROUP				-1:0]w_sdr_DQM;
+wire	[DQ_GROUP	*DQ_WIDTH	-1:0]w_sdr_DQ;
+
+genvar i, j;
+generate
+	for (i=0; i<DQ_GROUP*DQ_WIDTH; i=i+1)
+	begin: DQ_map
+		assign	w_sdr_DQ[i]	=	(w_sdr_DATA_oe[i])?
+									w_sdr_DATA[i]:1'bz;
+	end
+
+	for (j=0; j<DQ_GROUP; j=j+1)
+	begin : mem_inst
+        generic_sdr inst_sdr
+        (
+        	.Dq(w_sdr_DQ[((j+1)*(DQ_WIDTH))-1:((j)*DQ_WIDTH)]),
+        	.Addr(w_sdr_ADDR[ROW_WIDTH-1:0]),
+        	.Ba(w_sdr_BA[BA_WIDTH-1:0]),
+        	.Clk(~r_sdrclk),
+        	.Cke(w_sdr_CKE),
+        	.Cs_n(w_sdr_n_CS),
+        	.Ras_n(w_sdr_n_RAS),
+        	.Cas_n(w_sdr_n_CAS),
+        	.We_n(w_sdr_n_WE),
+        	.Dqm(w_sdr_DQM[j])
+        );
+    end
+endgenerate
+
 
 endmodule