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This commit is contained in:
Byron Lathi
2023-10-15 18:58:25 -07:00
parent 76aea3180a fd4dbfaf81
commit 155e89240a
48 changed files with 2545 additions and 705 deletions
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27
hw/efinix_fpga/init_env.sh
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@@ -1,27 +0,0 @@
# # This stuff will install efinity per machine, per project.
# # That would be a lot of wasted storage
# ENV=".env/$HOSTNAME"
# if [ ! -d "$ENV" ]; then
# mkdir -p "$ENV"
# fi
# if [ ! -f "$ENV/efinity-2023.1.150-rhe-x64.tar.bz2" ]; then
# scp 192.168.50.101:/export/scratch/efinity-2023.1.150-rhe-x64.tar.bz2 "$ENV"
# fi
# if [ ! -d "$ENV/efinity" ]; then
# pv "$ENV/efinity-2023.1.150-rhe-x64.tar.bz2" | tar xj --directory "$ENV"
# scp 192.168.50.101:/export/scratch/libffi.so.6 "$ENV/efinity/2023.1/lib/"
# fi
# source "$ENV/efinity/2023.1/bin/setup.sh"
# export PATH=$PATH:"$EFXPT_HOME/bin"
source $EFX_SETUP
# python -m venv .user_venv --system-site-packages
# . .user_venv/bin/activate
# pip install -r requirements.txt

426
hw/efinix_fpga/init_hex.mem
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@@ -1,9 +1,9 @@
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FA 20 98 F6 85 06 86 07 20 6F F6 A0 01 B1 18 AA
88 B1 18 60 A0 00 84 0C 84 0D B1 1A 38 E9 30 90
2C C9 0A B0 28 20 52 F6 48 A5 0C A6 0D 06 0C 26
0D 06 0C 26 0D 65 0C 85 0C 8A 65 0D 85 0D 06 0C
26 0D 68 65 0C 85 0C 90 D1 E6 0D B0 CD A5 0C A6
0D 60 AC 51 92 EE 51 92 99 52 92 60 A9 52 A2 92
18 6D 51 92 90 01 E8 4C CC FC A5 1C A6 1D 4C CC
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FA F6 AD 66 92 AE 67 92 20 CC FC AD 68 92 AE 69
92 20 CC FC 4C 02 92 84 0C 20 8A FB 20 EC F6 A5
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86 19 20 0D FB 85 1A 86 1B 20 0D FB 85 1C 86 1D
A9 00 A8 91 1C C8 91 1C C8 B1 1C 8D 03 92 C8 B1
1C 8D 04 92 A5 1A 85 0C A5 1B 85 0D A0 00 B1 1A
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1A 85 1A 90 02 E6 1B 38 E5 0C 85 0E A5 1B E5 0D
85 0F 05 0E F0 25 20 F3 FA A0 05 A5 1D 91 04 88
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00 A2 0B 9D 46 92 CA 10 FA B1 1A C9 2D D0 05 8E
46 92 F0 19 C9 2B D0 05 8E 47 92 F0 10 C9 20 D0
05 8E 48 92 F0 07 C9 23 D0 09 8E 49 92 20 52 F6
4C F9 F7 A2 20 C9 30 D0 06 AA 20 52 F6 B1 1A 8E
4A 92 C9 2A D0 09 20 52 F6 20 98 F6 4C 42 F8 20
A4 F6 8D 4B 92 8E 4C 92 8C 4D 92 8C 4E 92 B1 1A
C9 2E D0 1B 20 52 F6 B1 1A C9 2A D0 09 20 52 F6
20 98 F6 4C 69 F8 20 A4 F6 8D 4D 92 8E 4E 92 B1
1A C9 7A F0 19 C9 68 F0 15 C9 74 F0 11 C9 6A F0
08 C9 4C F0 04 C9 6C D0 0B A9 FF 8D 4F 92 20 52
F6 4C 6F F8 8C 51 92 A2 52 8E 66 92 A2 92 8E 67
92 20 52 F6 C9 63 D0 0D 20 98 F6 8D 52 92 A2 00
A9 01 4C 9B F9 C9 64 F0 04 C9 69 D0 2D A2 00 AD
48 92 F0 02 A2 20 AD 47 92 F0 02 A2 2B 8E 50 92
20 86 F6 A4 07 30 0B AC 50 92 F0 06 8C 52 92 EE
51 92 A0 0A 20 27 F7 4C 92 F9 C9 6E D0 15 20 98
F6 85 0C 86 0D A0 00 B1 1C 91 0C C8 B1 1C 91 0C
4C 74 F7 C9 6F D0 27 20 86 F6 AC 49 92 F0 17 48
86 14 05 14 05 06 05 07 0D 4D 92 0D 4E 92 F0 06
A9 30 20 E2 F6 68 A0 08 20 27 F7 4C 92 F9 C9 70
D0 0D A2 00 8E 4F 92 E8 8E 49 92 A9 78 D0 27 C9
73 D0 0C 20 98 F6 8D 66 92 8E 67 92 4C 92 F9 C9
75 D0 0B 20 7B F6 A0 0A 20 34 F7 4C 92 F9 C9 78
F0 04 C9 58 D0 29 48 AD 49 92 F0 0A A9 30 20 E2
F6 A9 58 20 E2 F6 20 7B F6 A0 10 20 34 F7 68 C9
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AA 49 FF 8D 4C 92 8A 49 FF 8D 4B 92 AD 46 92 D0
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AA 68 60 C8 48 18 98 65 04 85 04 90 02 E6 05 68
60 A0 FF E0 80 B0 02 A0 00 84 06 84 07 60 E0 00
D0 06 AA D0 03 A9 01 60 A2 00 8A 60 A0 00 F0 07
A9 52 A2 F0 4C 05 92 60 A9 00 85 0C A9 F0 85 0D
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E8 F0 0D B1 0C 91 0E C8 D0 F6 E6 0D E6 0F D0 F0
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A6 05 90 01 E8 86 0D A0 01 B1 0C AA 88 B1 0C 20
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EE 60 E0 00 D0 15 4A AA BD 5A FE 90 05 4A 4A 4A
4A 18 29 0F AA BD 4F FE A2 00 60 38 A9 00 AA 60
A4 04 D0 02 C6 05 C6 04 60 A5 04 38 E9 02 85 04
90 01 60 C6 05 60 A5 04 38 E9 04 85 04 90 01 60
C6 05 60 A5 04 38 E9 06 85 04 90 01 60 C6 05 60
A5 04 38 E9 07 85 04 90 01 60 C6 05 60 A0 01 B1
04 AA 88 B1 04 E6 04 F0 05 E6 04 F0 03 60 E6 04
E6 05 60 A0 03 4C 04 FA A0 05 4C 04 FA A0 08 4C
04 FA 85 0C 86 0D A2 00 B1 0C 60 A0 01 B1 04 AA
88 B1 04 60 A0 03 B1 04 85 07 88 B1 04 85 06 88
B1 04 AA 88 B1 04 60 A2 00 18 65 04 48 8A 65 05
AA 68 60 18 49 FF 69 01 48 8A 49 FF 69 00 AA A5
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60 A9 00 AA A0 00 84 06 84 07 48 20 E6 FA A0 03
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1D A9 2D A0 00 91 0E E6 0E D0 02 E6 0F A5 0C A6
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48 A0 20 A9 00 06 0C 26 0D 26 06 26 07 2A C5 14
90 04 E5 14 E6 0C 88 D0 EC A8 B9 33 FE 48 A5 0C
05 0D 05 06 05 07 D0 D9 A0 00 68 91 0E F0 03 C8
D0 F8 A5 10 A6 11 60 D0 06 A2 00 8A 60 D0 FA A2
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CA FC A0 00 B1 04 A4 04 F0 07 C6 04 A0 00 91 04
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54
hw/efinix_fpga/simulation/Makefile
View File

@@ -1,20 +1,48 @@
TARGETS= timer interrupt_controller spi_controller
TB=$(patsubst %, %_tb.sv, $(TARGETS))
SRCS=$(shell find src/ -type f -name "*.*v")
SRCS+=$(shell find ../ip/ -type f -name "*.*v" -not \( -name "*tmpl*" \))
SRCS+=$(shell find ../src/ -type f -name "*.*v")
all: $(TARGETS)
INC=$(shell find include/ -type f)
timer: timer_tb.sv
iverilog -g2005-sv -s sim -o $@ $@_tb.sv ../$@.sv
TEST_PROGRAM_NAME?=loop_test
TEST_FOLDER?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)
TEST_PROGRAM?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).hex
spi_controller: spi_controller_tb.sv ../spi_controller.sv
iverilog -g2005-sv -s sim -o $@ $@_tb.sv ../$@.sv
SD_IMAGE_PATH?=$(REPO_TOP)/sw/script/fs.fat.hex
interrupt_controller: interrupt_controller_tb.sv
iverilog -g2005-sv -s sim -o $@ $@_tb.sv ../$@.sv
#TODO implement something like sources.list
TOP_MODULE=sim_top
TARGET=sim_top
INIT_MEM=init_hex.mem
SD_IMAGE=sd_image.mem
FLAGS=-DSIM -DRTL_SIM
all: sim
.PHONY: sim
sim: $(TARGET)
vvp $(TARGET) -fst
.PHONY: full_sim
full_sim: $(TARGET) $(SD_IMAGE)
vvp $(TARGET) -fst
$(TARGET): $(INIT_MEM) $(SRCS)
iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
$(INIT_MEM):
$(MAKE) -C $(TEST_FOLDER)
cp $(TEST_PROGRAM) ./init_hex.mem
# The script that makes this file uses relative paths
$(SD_IMAGE):
sh $(REPO_TOP)/sw/script/create_verilog_image.sh
cp $(SD_IMAGE_PATH) $(SD_IMAGE)
.PHONY: clean
clean:
rm -f $(TARGETS)
rm -f *.vcd
rm -f *.vvp
rm -rf $(TARGET)
rm -rf $(INIT_MEM)
rm -rf $(SD_IMAGE)

80
hw/efinix_fpga/simulation/include/super6502_sdram_controller_define.vh Normal file
View File

@@ -0,0 +1,80 @@
// =============================================================================
// Generated by efx_ipmgr
// Version: 2023.1.150
// IP Version: 5.0
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam fSYS_MHz = 100;
localparam fCK_MHz = 200;
localparam tIORT_u = 2;
localparam CL = 3;
localparam BL = 1;
localparam DDIO_TYPE = "SOFT";
localparam DQ_WIDTH = 8;
localparam DQ_GROUP = 2;
localparam BA_WIDTH = 2;
localparam ROW_WIDTH = 13;
localparam COL_WIDTH = 9;
localparam tPWRUP = 200000;
localparam tRAS = 44;
localparam tRAS_MAX = 120000;
localparam tRC = 66;
localparam tRCD = 20;
localparam tREF = 64000000;
localparam tRFC = 66;
localparam tRP = 20;
localparam tWR = 2;
localparam tMRD = 2;
localparam SDRAM_MODE = "Native";
localparam DATA_RATE = 2;
localparam AXI_AWADDR_WIDTH = 24;
localparam AXI_WDATA_WIDTH = 32;
localparam AXI_ARADDR_WIDTH = 24;
localparam AXI_RDATA_WIDTH = 32;
localparam AXI_AWID_WIDTH = 4;
localparam AXI_AWUSER_WIDTH = 2;
localparam AXI_WUSER_WIDTH = 2;
localparam AXI_BID_WIDTH = 4;
localparam AXI_BUSER_WIDTH = 2;
localparam AXI_ARID_WIDTH = 4;
localparam AXI_ARUSER_WIDTH = 3;
localparam AXI_RUSER_WIDTH = 3;

76
hw/efinix_fpga/simulation/interrupt_controller_tb.sv
View File

@@ -1,76 +0,0 @@
module sim();
timeunit 10ns;
timeprecision 1ns;
logic clk;
logic reset;
logic [2:0] addr;
logic [7:0] i_data;
logic [7:0] o_data;
logic cs;
logic rwb;
logic irqb_master;
logic irqb0, irqb1, irqb2, irqb3, irqb4, irqb5, irqb6, irqb7;
interrupt_controller dut(
.*);
always #100 clk = clk === 1'b0;
task write_reg(input logic [2:0] _addr, input logic [7:0] _data);
@(negedge clk);
cs <= '1;
addr <= _addr;
rwb <= '0;
i_data <= '1;
@(posedge clk);
i_data <= _data;
@(negedge clk);
cs <= '0;
rwb <= '1;
endtask
task read_reg(input logic [2:0] _addr, output logic [7:0] _data);
@(negedge clk);
cs <= '1;
addr <= _addr;
rwb <= '1;
i_data <= '1;
@(posedge clk);
_data <= o_data;
@(negedge clk);
cs <= '0;
rwb <= '1;
endtask
initial
begin
$dumpfile("interrupt_controller.vcd");
$dumpvars(0,sim);
end
initial begin
reset <= '1;
irqb0 <= '1;
irqb1 <= '1;
irqb2 <= '1;
irqb3 <= '1;
irqb4 <= '1;
irqb5 <= '1;
irqb6 <= '1;
irqb7 <= '1;
repeat(5) @(posedge clk);
reset <= '0;
repeat(5) @(posedge clk);
irqb0 <= '0;
repeat(5) @(posedge clk);
$finish();
end
endmodule

102
hw/efinix_fpga/simulation/spi_controller_tb.sv
View File

@@ -1,102 +0,0 @@
module sim();
timeunit 10ns;
timeprecision 1ns;
logic clk_50;
logic i_clk;
logic i_rst;
logic i_cs;
logic i_rwb;
logic [1:0] i_addr;
logic [7:0] i_data;
logic [7:0] o_data;
logic o_spi_cs;
logic o_spi_clk;
logic o_spi_mosi;
logic i_spi_miso;
spi_controller dut(.*);
always #1 clk_50 = clk_50 === 1'b0;
always #100 i_clk = i_clk === 1'b0;
task write_reg(input logic [2:0] _addr, input logic [7:0] _data);
@(negedge i_clk);
i_cs <= '1;
i_addr <= _addr;
i_rwb <= '0;
i_data <= '1;
@(posedge i_clk);
i_data <= _data;
@(negedge i_clk);
i_cs <= '0;
i_rwb <= '1;
endtask
task read_reg(input logic [2:0] _addr, output logic [7:0] _data);
@(negedge i_clk);
i_cs <= '1;
i_addr <= _addr;
i_rwb <= '1;
i_data <= '1;
@(posedge i_clk);
_data <= o_data;
@(negedge i_clk);
i_cs <= '0;
i_rwb <= '1;
endtask
initial
begin
$dumpfile("spi_controller.vcd");
$dumpvars(0,sim);
end
logic [7:0] data;
initial begin
i_rst <= '1;
repeat(5) @(posedge i_clk);
i_cs <= '0;
i_rwb <= '1;
i_addr <= '0;
i_rst <= '0;
repeat(5) @(posedge i_clk);
write_reg(3, 1);
write_reg(2, 8'hFF);
data = (1 << 7);
while(data & (1 << 7)) begin
read_reg(3, data);
end
write_reg(3, 0);
read_reg(1, data);
assert(data == 8'h55);
repeat(50) @(posedge i_clk);
$finish();
end
logic [7:0] _spi_device_data;
initial begin
_spi_device_data <= 8'h55;
end
always @(edge o_spi_clk) begin
if (o_spi_cs == '0) begin
if (o_spi_clk == '1)
i_spi_miso <= _spi_device_data[7];
if (o_spi_clk == '0)
_spi_device_data <= _spi_device_data << 1;
end
end
endmodule

1145
hw/efinix_fpga/simulation/src/generic_sdr.v Normal file
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File diff suppressed because it is too large Load Diff

177
hw/efinix_fpga/simulation/src/sim_top.sv Normal file
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@@ -0,0 +1,177 @@
`timescale 1ns/1ps
module sim_top();
`include "include/super6502_sdram_controller_define.vh"
logic r_sysclk, r_sdrclk, r_clk_50, r_clk_cpu;
// clk_100
initial begin
r_sysclk <= '1;
forever begin
#5 r_sysclk <= ~r_sysclk;
end
end
// clk_200
initial begin
r_sdrclk <= '1;
forever begin
#2.5 r_sdrclk <= ~r_sdrclk;
end
end
// clk_50
initial begin
r_clk_50 <= '1;
forever begin
#10 r_clk_50 <= ~r_clk_50;
end
end
// clk_cpu
initial begin
r_clk_cpu <= '1;
forever begin
#125 r_clk_cpu <= ~r_clk_cpu;
end
end
// initial begin
// #275000 $finish();
// end
initial begin
$dumpfile("sim_top.vcd");
$dumpvars(0,sim_top);
end
logic button_reset;
initial begin
button_reset <= '0;
repeat(10) @(r_clk_cpu);
button_reset <= '1;
repeat(1000000) @(r_clk_cpu);
$finish();
end
logic w_cpu_reset;
logic [15:0] w_cpu_addr;
logic [7:0] w_cpu_data_from_cpu, w_cpu_data_from_dut;
logic w_cpu_rdy;
logic w_cpu_we;
logic w_cpu_phi2;
//TODO: this
cpu_65c02 u_cpu(
.phi2(w_cpu_phi2),
.reset(~w_cpu_reset),
.AB(w_cpu_addr),
.RDY(w_cpu_rdy),
.IRQ('0),
.NMI('0),
.DI_s1(w_cpu_data_from_dut),
.DO(w_cpu_data_from_cpu),
.WE(w_cpu_we)
);
logic w_dut_uart_rx, w_dut_uart_tx;
sim_uart u_sim_uart(
.clk_50(r_clk_50),
.reset(~w_cpu_reset),
.rx_i(w_dut_uart_tx),
.tx_o(w_dut_uart_rx)
);
logic w_sd_cs;
logic w_spi_clk;
logic w_spi_mosi;
logic w_spi_miso;
sd_card_emu u_sd_card_emu(
.rst(~w_cpu_reset),
.clk(w_spi_clk),
.cs(w_sd_cs),
.mosi(w_spi_mosi),
.miso(w_spi_miso)
);
super6502 u_dut(
.i_sysclk(r_sysclk),
.i_sdrclk(r_sdrclk),
.i_tACclk(~r_sdrclk),
.clk_50(r_clk_50),
.clk_cpu(r_clk_cpu),
.button_reset(button_reset),
.cpu_resb(w_cpu_reset),
.cpu_addr(w_cpu_addr),
.cpu_data_out(w_cpu_data_from_dut),
.cpu_data_in(w_cpu_data_from_cpu),
.cpu_rwb(~w_cpu_we),
.cpu_rdy(w_cpu_rdy),
.cpu_phi2(w_cpu_phi2),
.uart_rx(w_dut_uart_rx),
.uart_tx(w_dut_uart_tx),
.sd_cs(w_sd_cs),
.spi_clk(w_spi_clk),
.spi_mosi(w_spi_mosi),
.spi_miso(w_spi_miso),
.o_sdr_CKE(w_sdr_CKE),
.o_sdr_n_CS(w_sdr_n_CS),
.o_sdr_n_WE(w_sdr_n_WE),
.o_sdr_n_RAS(w_sdr_n_RAS),
.o_sdr_n_CAS(w_sdr_n_CAS),
.o_sdr_BA(w_sdr_BA),
.o_sdr_ADDR(w_sdr_ADDR),
.i_sdr_DATA(w_sdr_DQ),
.o_sdr_DATA(w_sdr_DATA),
.o_sdr_DATA_oe(w_sdr_DATA_oe),
.o_sdr_DQM(w_sdr_DQM)
);
wire w_sdr_CKE;
wire w_sdr_n_CS;
wire w_sdr_n_WE;
wire w_sdr_n_RAS;
wire w_sdr_n_CAS;
wire [BA_WIDTH -1:0]w_sdr_BA;
wire [ROW_WIDTH -1:0]w_sdr_ADDR;
wire [DQ_GROUP *DQ_WIDTH -1:0]w_sdr_DATA;
wire [DQ_GROUP *DQ_WIDTH -1:0]w_sdr_DATA_oe;
wire [DQ_GROUP -1:0]w_sdr_DQM;
wire [DQ_GROUP *DQ_WIDTH -1:0]w_sdr_DQ;
genvar i, j;
generate
for (i=0; i<DQ_GROUP*DQ_WIDTH; i=i+1)
begin: DQ_map
assign w_sdr_DQ[i] = (w_sdr_DATA_oe[i])?
w_sdr_DATA[i]:1'bz;
end
for (j=0; j<DQ_GROUP; j=j+1)
begin : mem_inst
generic_sdr inst_sdr
(
.Dq(w_sdr_DQ[((j+1)*(DQ_WIDTH))-1:((j)*DQ_WIDTH)]),
.Addr(w_sdr_ADDR[ROW_WIDTH-1:0]),
.Ba(w_sdr_BA[BA_WIDTH-1:0]),
.Clk(~r_sdrclk),
.Cke(w_sdr_CKE),
.Cs_n(w_sdr_n_CS),
.Ras_n(w_sdr_n_RAS),
.Cas_n(w_sdr_n_CAS),
.We_n(w_sdr_n_WE),
.Dqm(w_sdr_DQM[j])
);
end
endgenerate
endmodule

43
hw/efinix_fpga/simulation/src/sim_uart/sim_uart.sv Normal file
View File

@@ -0,0 +1,43 @@
module sim_uart(
input clk,
input clk_50,
input reset,
input [7:0] i_data,
input rx_i,
output tx_o
);
logic tx_busy, rx_busy;
logic rx_data_valid, rx_error, rx_parity_error;
logic baud_x16_ce;
logic tx_en;
logic [7:0] tx_data, rx_data;
uart u_uart(
.tx_o ( tx_o ),
.rx_i ( rx_i ),
.tx_busy ( tx_busy ),
.rx_data ( rx_data ),
.rx_data_valid ( rx_data_valid ),
.rx_error ( rx_error ),
.rx_parity_error ( rx_parity_error ),
.rx_busy ( rx_busy ),
.baud_x16_ce ( baud_x16_ce ),
.clk ( clk_50 ),
.reset ( reset ),
.tx_data ( tx_data ),
.baud_rate ( baud_rate ),
.tx_en ( tx_en )
);
always @(posedge baud_x16_ce) begin
if (rx_data_valid)
$display("UART: %c", rx_data);
end
endmodule

1
hw/efinix_fpga/simulation/src/verilog-6502 Submodule

Submodule hw/efinix_fpga/simulation/src/verilog-6502 added at aaf4c084ef

1
hw/efinix_fpga/simulation/src/verilog-sd-emulator Submodule

Submodule hw/efinix_fpga/simulation/src/verilog-sd-emulator added at 390b7221db

75
hw/efinix_fpga/simulation/timer_tb.sv
View File

@@ -1,75 +0,0 @@
module sim();
timeunit 10ns;
timeprecision 1ns;
logic clk;
logic rwb;
logic clk_50;
logic reset;
logic [2:0] addr;
logic [7:0] i_data;
logic [7:0] o_data;
logic cs;
logic irq;
timer dut(
.*);
always #1 clk_50 = clk_50 === 1'b0;
always #100 clk = clk === 1'b0;
task write_reg(input logic [2:0] _addr, input logic [7:0] _data);
@(negedge clk);
cs <= '1;
addr <= _addr;
rwb <= '0;
i_data <= '1;
@(posedge clk);
i_data <= _data;
@(negedge clk);
cs <= '0;
rwb <= '1;
endtask
task read_reg(input logic [2:0] _addr, output logic [7:0] _data);
@(negedge clk);
cs <= '1;
addr <= _addr;
rwb <= '1;
i_data <= '1;
@(posedge clk);
_data <= o_data;
@(negedge clk);
cs <= '0;
rwb <= '1;
endtask
initial
begin
$dumpfile("timer.vcd");
$dumpvars(0,sim);
end
logic [7:0] read_data;
initial begin
reset <= '1;
repeat(5) @(posedge clk);
reset <= '0;
write_reg(5, 16);
repeat(1024) @(posedge clk);
repeat(10) begin
read_reg(0, read_data);
$display("Read: %d", read_data);
repeat(1024) @(posedge clk);
end
$finish();
end
endmodule

26
hw/efinix_fpga/src/addr_decode.sv
View File

@@ -1,26 +0,0 @@
module addr_decode
(
input [24:0] i_addr,
input config_reg_sel,
output o_rom_cs,
output o_leds_cs,
output o_timer_cs,
output o_multiplier_cs,
output o_divider_cs,
output o_uart_cs,
output o_spi_cs,
output o_sdram_cs
);
assign o_rom_cs = (i_addr >= 25'hf000 && i_addr <= 25'hffff) && ~config_reg_sel;
assign o_timer_cs = (i_addr >= 25'heff8 && i_addr <= 25'heffb) && ~config_reg_sel;
assign o_multiplier_cs = (i_addr >= 25'heff0 && i_addr <= 25'heff7) && ~config_reg_sel;
assign o_divider_cs = (i_addr >= 25'hefe8 && i_addr <= 25'hefef) && ~config_reg_sel;
assign o_uart_cs = (i_addr >= 25'hefe6 && i_addr <= 25'hefe7) && ~config_reg_sel;
assign o_spi_cs = (i_addr >= 25'hefd8 && i_addr <= 25'hefdb) && ~config_reg_sel;
assign o_leds_cs = (i_addr == 25'hefff) && ~config_reg_sel;
assign o_sdram_cs = (i_addr < 25'he000 || i_addr >= 25'h10000) && ~config_reg_sel;
endmodule

110
hw/efinix_fpga/src/sdram_adapter.sv
View File

@@ -70,10 +70,11 @@ assign o_sdr_DQM = w_sdr_DQM[0+:2];
// But basically if we are in access, and cpuclk goes low, go back to wait.
// If something actually happened, we would be in one of the read/write states.
enum bit [1:0] {ACCESS, READ_WAIT, WRITE_WAIT, WAIT} state, next_state;
enum bit [2:0] {ACCESS, PRE_READ, READ_WAIT, PRE_WRITE, WRITE_WAIT, WAIT} state, next_state;
logic w_read, w_write, w_last;
logic [23:0] w_addr, r_addr;
logic [23:0] w_read_addr, w_write_addr;
logic [23:0] r_read_addr, r_write_addr;
logic [31:0] w_data_i, w_data_o;
logic [3:0] w_dm, r_dm;
@@ -86,25 +87,15 @@ logic [31:0] r_write_data;
logic [1:0] counter, next_counter;
always @(posedge i_sysclk) begin
if (i_arst) begin
state <= WAIT;
counter <= '0;
end else begin
state <= next_state;
counter <= next_counter;
r_write_data <= w_data_i;
r_addr <= w_addr;
r_dm <= w_dm;
end
if (w_data_valid)
o_data <= _data;
end
logic [7:0] o_data_next;
logic [23:0] addr_mux_out;
logic slow_mem;
logic r_wait;
logic _r_wait;
assign o_wait = r_wait;
assign o_wait = (r_wait | slow_mem) & i_cs;
// we need to assert rdy low until a falling edge if a reset happens
@@ -126,6 +117,20 @@ always @(posedge i_sysclk or posedge i_arst) begin
end
end
end
if (i_arst) begin
state <= WAIT;
counter <= '0;
end else begin
state <= next_state;
counter <= next_counter;
r_write_data <= w_data_i;
r_read_addr <= w_read_addr;
r_write_addr <= w_write_addr;
r_dm <= w_dm;
end
o_data <= o_data_next;
end
//because of timing issues, We really need to trigger
@@ -157,10 +162,12 @@ end
always_comb begin
slow_mem = '0;
next_state = state;
next_counter = counter;
w_addr = '0;
w_read_addr = '0;
w_write_addr = '0;
w_dm = '0;
w_read = '0;
w_write = '0;
@@ -171,65 +178,81 @@ always_comb begin
unique case (state)
WAIT: begin
if (i_cs & i_cpuclk)
if (i_cs & ~i_cpuclk)
next_state = ACCESS;
end
ACCESS: begin
// only do something if selected
if (i_cs) begin
w_addr = {{i_addr[24:2]}, {1'b0}};; // divide by 2, set last bit to 0
w_read_addr = {{i_addr[24:2]}, {1'b0}}; // divide by 2, set last bit to 0
w_write_addr = {{i_addr[24:2]}, {1'b0}}; // divide by 2, set last bit to 0
addr_mux_out = w_read_addr;
if (i_rwb) begin //read
w_read = '1;
w_last = '1;
// dm is not needed for reads?
if (w_rd_ack) next_state = READ_WAIT;
next_state = PRE_READ;
end else begin //write
w_data_i = i_data << (8*i_addr[1:0]);
//w_data_i = {4{i_data}}; //does anything get through?
w_dm = ~(4'b1 << i_addr[1:0]);
if (~i_cpuclk) begin
w_write = '1;
w_last = '1;
next_state = WRITE_WAIT;
end
next_state = PRE_WRITE;
end
end
end
PRE_WRITE: begin
w_data_i = r_write_data;
w_write_addr = r_write_addr;
addr_mux_out = w_write_addr;
w_dm = r_dm;
//w_data_i = {4{i_data}}; //does anything get through?
if (~i_cpuclk) begin
w_write = '1;
w_last = '1;
next_state = WRITE_WAIT;
end
end
WRITE_WAIT: begin
// stay in this state until write is acknowledged.
w_write_addr = r_write_addr;
addr_mux_out = w_write_addr;
w_write = '1;
w_last = '1;
w_data_i = r_write_data;
w_dm = r_dm;
w_addr = r_addr;
if (w_wr_ack) next_state = WAIT;
end
PRE_READ: begin
w_read_addr = r_read_addr;
addr_mux_out = w_read_addr;
w_read = '1;
w_last = '1;
slow_mem = '1;
// dm is not needed for reads?
if (w_rd_ack) next_state = READ_WAIT;
end
READ_WAIT: begin
w_read_addr = r_read_addr;
addr_mux_out = w_read_addr;
slow_mem = '1;
if (w_rd_valid) begin
w_data_valid = '1;
_data = w_data_o[8*i_addr[1:0]+:8];
end
// you must wait until the next cycle!
if (~i_cpuclk) begin
if (w_data_valid) begin
next_state = WAIT;
end
end
endcase
end
//this seems scuffed
logic [23:0] addr_mux_out;
always_comb begin
if (state == ACCESS) begin
addr_mux_out = w_addr;
if (w_data_valid) begin
o_data_next = _data;
end else begin
addr_mux_out = r_addr;
o_data_next = o_data;
end
end
@@ -245,10 +268,11 @@ logic [3:0] o_dbg_BA;
logic [25:0] o_dbg_ADDR;
logic [31:0] o_dbg_DATA_out;
logic [31:0] o_dbg_DATA_in;
logic o_sdr_init_done;
logic sdr_init_done;
logic [3:0] o_sdr_state;
assign o_ref_req = o_dbg_ref_req;
assign o_sdr_init_done = sdr_init_done;
sdram_controller u_sdram_controller(
@@ -265,7 +289,7 @@ sdram_controller u_sdram_controller(
.i_din(r_write_data), //Data to write to SDRAM. Twice normal width when running at half speed (hence the even addresses)
.i_dm(r_dm), //dm (r_dm)
.o_dout(w_data_o), //Data read from SDRAM, doubled as above.
.o_sdr_init_done(o_sdr_init_done), //Indicates that the SDRAM initialization is done.
.o_sdr_init_done(sdr_init_done), //Indicates that the SDRAM initialization is done.
.o_wr_ack(w_wr_ack), //Write acknowledge, handshake with we
.o_rd_ack(w_rd_ack), //Read acknowledge, handshake with re
.o_rd_valid(w_rd_valid),//Read valid. The data on o_dout is valid

1
hw/efinix_fpga/src/spi_controller.sv
View File

@@ -90,6 +90,7 @@ always_comb begin
1: o_data = r_input_data;
2:;
3: o_data = {active, r_control[6:0]};
default: o_data = 'x;
endcase
end

48
hw/efinix_fpga/src/super6502.sv
View File

@@ -15,7 +15,7 @@ module super6502
input button_reset,
input pll_cpu_locked,
input clk_50,
input clk_2,
input clk_cpu,
input logic [15:0] cpu_addr,
output logic [7:0] cpu_data_out,
output logic [7:0] cpu_data_oe,
@@ -60,11 +60,11 @@ assign cpu_nmib = '1;
logic w_wait;
assign cpu_rdy = ~w_wait;
assign cpu_phi2 = clk_2;
assign cpu_phi2 = clk_cpu;
logic w_sdr_init_done;
always @(posedge clk_2) begin
always @(posedge clk_cpu) begin
if (button_reset == '0) begin
cpu_resb <= '0;
end
@@ -94,18 +94,6 @@ logic w_uart_cs;
logic w_mapper_cs;
logic w_spi_cs;
addr_decode u_addr_decode(
.i_addr(w_sdram_addr),
.config_reg_sel(w_control_reg_cs),
.o_rom_cs(w_rom_cs),
.o_leds_cs(w_leds_cs),
.o_timer_cs(w_timer_cs),
.o_multiplier_cs(w_multiplier_cs),
.o_divider_cs(w_divider_cs),
.o_uart_cs(w_uart_cs),
.o_spi_cs(w_spi_cs),
.o_sdram_cs(w_sdram_cs)
);
logic [7:0] w_rom_data_out;
logic [7:0] w_leds_data_out;
@@ -118,6 +106,16 @@ logic [7:0] w_mapper_data_out;
logic [7:0] w_sdram_data_out;
always_comb begin
w_rom_cs = cpu_addr >= 16'hf000 && cpu_addr <= 16'hffff;
w_timer_cs = cpu_addr >= 16'heff8 && cpu_addr <= 16'heffb;
w_multiplier_cs = cpu_addr >= 16'heff0 && cpu_addr <= 16'heff7;
w_divider_cs = cpu_addr >= 16'hefe8 && cpu_addr <= 16'hefef;
w_uart_cs = cpu_addr >= 16'hefe6 && cpu_addr <= 16'hefe7;
w_spi_cs = cpu_addr >= 16'hefd8 && cpu_addr <= 16'hefdb;
w_leds_cs = cpu_addr == 16'hefff;
w_sdram_cs = cpu_addr < 16'he000;
if (w_rom_cs)
cpu_data_out = w_rom_data_out;
else if (w_leds_cs)
@@ -154,13 +152,13 @@ mapper u_mapper(
);
rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom(
.addr(w_sdram_addr[11:0]),
.clk(clk_2),
.addr(cpu_addr[11:0]),
.clk(clk_cpu),
.data(w_rom_data_out)
);
leds u_leds(
.clk(clk_2),
.clk(clk_cpu),
.i_data(cpu_data_in),
.o_data(w_leds_data_out),
.cs(w_leds_cs),
@@ -171,7 +169,7 @@ leds u_leds(
logic w_timer_irqb;
timer u_timer(
.clk(clk_2),
.clk(clk_cpu),
.reset(~cpu_resb),
.i_data(cpu_data_in),
.o_data(w_timer_data_out),
@@ -182,7 +180,7 @@ timer u_timer(
);
multiplier u_multiplier(
.clk(clk_2),
.clk(clk_cpu),
.reset(~cpu_resb),
.i_data(cpu_data_in),
.o_data(w_multiplier_data_out),
@@ -192,7 +190,7 @@ multiplier u_multiplier(
);
divider_wrapper u_divider(
.clk(clk_2),
.clk(clk_cpu),
.divclk(clk_50),
.reset(~cpu_resb),
.i_data(cpu_data_in),
@@ -205,7 +203,7 @@ divider_wrapper u_divider(
logic w_uart_irqb;
uart_wrapper u_uart(
.clk(clk_2),
.clk(clk_cpu),
.clk_50(clk_50),
.reset(~cpu_resb),
.i_data(cpu_data_in),
@@ -219,7 +217,7 @@ uart_wrapper u_uart(
);
spi_controller spi_controller(
.i_clk(clk_2),
.i_clk(clk_cpu),
.i_rst(~cpu_resb),
.i_cs(w_spi_cs),
.i_rwb(cpu_rwb),
@@ -235,7 +233,7 @@ spi_controller spi_controller(
sdram_adapter u_sdram_adapter(
.i_cpuclk(clk_2),
.i_cpuclk(clk_cpu),
.i_arst(~button_reset),
.i_sysclk(i_sysclk),
.i_sdrclk(i_sdrclk),
@@ -265,7 +263,7 @@ sdram_adapter u_sdram_adapter(
);
interrupt_controller u_interrupt_controller(
.clk(clk_2),
.clk(clk_cpu),
.reset(~cpu_resb),
.i_data(cpu_data_in),
.o_data(w_irq_data_out),

2
hw/efinix_fpga/src/timer.sv
View File

@@ -123,6 +123,8 @@ always_comb begin
o_data = status;
end
default: o_data = 'x;
endcase
end

36
hw/efinix_fpga/src/uart_wrapper.sv
View File

@@ -46,7 +46,7 @@ enum bit [1:0] {READY, WAIT, TRANSMIT} state, next_state;
always_ff @(posedge clk_50) begin
if (reset) begin
state = READY;
state <= READY;
irqb <= '1;
end else begin
state <= next_state;
@@ -54,23 +54,27 @@ always_ff @(posedge clk_50) begin
end
always_ff @(negedge clk) begin
status[1] <= tx_busy | tx_en;
if (reset) begin
status <= '0;
end else begin
status[1] <= tx_busy | tx_en;
status[0] <= status[0] | rx_data_valid;
if (cs & ~addr & rwb) begin
status[0] <= 0;
end
status[0] <= status[0] | rx_data_valid;
if (cs & ~addr & rwb) begin
status[0] <= 0;
end
if (cs & ~rwb) begin
case (addr)
1'b0: begin
tx_data <= i_data;
end
if (cs & ~rwb) begin
case (addr)
1'b0: begin
tx_data <= i_data;
end
1'b1: begin
control <= i_data;
end
endcase
1'b1: begin
control <= i_data;
end
endcase
end
end
end
@@ -79,7 +83,7 @@ always_comb begin
case (addr)
1'b0: begin
o_data = rx_data;
end
end
1'b1: begin
o_data = status;

168
hw/efinix_fpga/super6502.xml
View File

@@ -1,106 +1,106 @@
<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502" description="" last_change_date="Mon Sep 18 2023 10:43:38 PM" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Sun October 15 2023 13:52:14" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion" />
<efx:device name="T20F256" />
<efx:timing_model name="C4" />
<efx:family name="Trion"/>
<efx:device name="T20F256"/>
<efx:timing_model name="C4"/>
</efx:device_info>
<efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008">
<efx:top_module name="super6502" />
<efx:design_file name="src/super6502.sv" version="default" library="default" />
<efx:design_file name="src/leds.sv" version="default" library="default" />
<efx:design_file name="src/addr_decode.sv" version="default" library="default" />
<efx:design_file name="src/sdram_adapter.sv" version="default" library="default" />
<efx:design_file name="src/timer.sv" version="default" library="default" />
<efx:design_file name="src/interrupt_controller.sv" version="default" library="default" />
<efx:design_file name="src/multiplier.sv" version="default" library="default" />
<efx:design_file name="src/divider_wrapper.sv" version="default" library="default" />
<efx:design_file name="src/uart_wrapper.sv" version="default" library="default" />
<efx:design_file name="src/sd_controller.sv" version="default" library="default" />
<efx:design_file name="src/crc7.sv" version="default" library="default" />
<efx:design_file name="src/rom.sv" version="default" library="default" />
<efx:design_file name="src/spi_controller.sv" version="default" library="default" />
<efx:design_file name="src/mapper.sv" version="default" library="default" />
<efx:top_vhdl_arch name="" />
<efx:top_module name="super6502"/>
<efx:design_file name="src/super6502.sv" version="default" library="default"/>
<efx:design_file name="src/leds.sv" version="default" library="default"/>
<efx:design_file name="src/addr_decode.sv" version="default" library="default"/>
<efx:design_file name="src/sdram_adapter.sv" version="default" library="default"/>
<efx:design_file name="src/timer.sv" version="default" library="default"/>
<efx:design_file name="src/interrupt_controller.sv" version="default" library="default"/>
<efx:design_file name="src/multiplier.sv" version="default" library="default"/>
<efx:design_file name="src/divider_wrapper.sv" version="default" library="default"/>
<efx:design_file name="src/uart_wrapper.sv" version="default" library="default"/>
<efx:design_file name="src/sd_controller.sv" version="default" library="default"/>
<efx:design_file name="src/crc7.sv" version="default" library="default"/>
<efx:design_file name="src/rom.sv" version="default" library="default"/>
<efx:design_file name="src/spi_controller.sv" version="default" library="default"/>
<efx:top_vhdl_arch name=""/>
</efx:design_info>
<efx:constraint_info>
<efx:sdc_file name="constraints/super6502.pt.sdc" />
<efx:inter_file name="" />
<efx:sdc_file name="constraints/super6502.pt.sdc"/>
<efx:inter_file name=""/>
</efx:constraint_info>
<efx:sim_info />
<efx:misc_info />
<efx:sim_info/>
<efx:misc_info/>
<efx:ip_info>
<efx:ip instance_name="sdram_controller" path="ip/sdram_controller/settings.json">
<efx:ip_src_file name="sdram_controller.v" />
<efx:ip_src_file name="sdram_controller.v"/>
</efx:ip>
<efx:ip instance_name="divider" path="ip/divider/settings.json">
<efx:ip_src_file name="divider.v" />
<efx:ip_src_file name="divider.v"/>
</efx:ip>
<efx:ip instance_name="uart" path="ip/uart/settings.json">
<efx:ip_src_file name="uart.v" />
<efx:ip_src_file name="uart.v"/>
</efx:ip>
</efx:ip_info>
<efx:synthesis tool_name="efx_map">
<efx:param name="work_dir" value="work_syn" value_type="e_string" />
<efx:param name="write_efx_verilog" value="on" value_type="e_bool" />
<efx:param name="mode" value="speed" value_type="e_option" />
<efx:param name="max_ram" value="-1" value_type="e_integer" />
<efx:param name="max_mult" value="-1" value_type="e_integer" />
<efx:param name="infer-clk-enable" value="3" value_type="e_option" />
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option" />
<efx:param name="fanout-limit" value="0" value_type="e_integer" />
<efx:param name="bram_output_regs_packing" value="1" value_type="e_option" />
<efx:param name="retiming" value="1" value_type="e_option" />
<efx:param name="seq_opt" value="1" value_type="e_option" />
<efx:param name="blast_const_operand_adders" value="1" value_type="e_option" />
<efx:param name="operator-sharing" value="0" value_type="e_option" />
<efx:param name="optimize-adder-tree" value="0" value_type="e_option" />
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option" />
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option" />
<efx:param name="min-sr-fanout" value="0" value_type="e_option" />
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option" />
<efx:param name="blackbox-error" value="1" value_type="e_option" />
<efx:param name="allow-const-ram-index" value="0" value_type="e_option" />
<efx:param name="hdl-compile-unit" value="1" value_type="e_option" />
<efx:param name="create-onehot-fsms" value="0" value_type="e_option" />
<efx:param name="min-ce-fanout" value="0" value_type="e_integer" />
<efx:param name="mult-decomp-retime" value="0" value_type="e_option" />
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option" />
<efx:param name="include" value="ip/sdram_controller" value_type="e_string" />
<efx:param name="include" value="ip/divider" value_type="e_string" />
<efx:param name="include" value="ip/uart" value_type="e_string" />
<efx:param name="work_dir" value="work_syn" value_type="e_string"/>
<efx:param name="write_efx_verilog" value="on" value_type="e_bool"/>
<efx:param name="mode" value="speed" value_type="e_option"/>
<efx:param name="max_ram" value="-1" value_type="e_integer"/>
<efx:param name="max_mult" value="-1" value_type="e_integer"/>
<efx:param name="infer-clk-enable" value="3" value_type="e_option"/>
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option"/>
<efx:param name="fanout-limit" value="0" value_type="e_integer"/>
<efx:param name="bram_output_regs_packing" value="1" value_type="e_option"/>
<efx:param name="retiming" value="1" value_type="e_option"/>
<efx:param name="seq_opt" value="1" value_type="e_option"/>
<efx:param name="blast_const_operand_adders" value="1" value_type="e_option"/>
<efx:param name="operator-sharing" value="0" value_type="e_option"/>
<efx:param name="optimize-adder-tree" value="0" value_type="e_option"/>
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option"/>
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option"/>
<efx:param name="min-sr-fanout" value="0" value_type="e_option"/>
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option"/>
<efx:param name="blackbox-error" value="1" value_type="e_option"/>
<efx:param name="allow-const-ram-index" value="0" value_type="e_option"/>
<efx:param name="hdl-compile-unit" value="1" value_type="e_option"/>
<efx:param name="create-onehot-fsms" value="0" value_type="e_option"/>
<efx:param name="min-ce-fanout" value="0" value_type="e_integer"/>
<efx:param name="mult-decomp-retime" value="0" value_type="e_option"/>
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option"/>
<efx:param name="include" value="ip/sdram_controller" value_type="e_string"/>
<efx:param name="include" value="ip/divider" value_type="e_string"/>
<efx:param name="include" value="ip/uart" value_type="e_string"/>
</efx:synthesis>
<efx:place_and_route tool_name="efx_pnr">
<efx:param name="work_dir" value="work_pnr" value_type="e_string" />
<efx:param name="verbose" value="off" value_type="e_bool" />
<efx:param name="load_delaym" value="on" value_type="e_bool" />
<efx:param name="optimization_level" value="NULL" value_type="e_option" />
<efx:param name="seed" value="1" value_type="e_integer" />
<efx:param name="placer_effort_level" value="2" value_type="e_option" />
<efx:param name="max_threads" value="-1" value_type="e_integer" />
<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
<efx:param name="verbose" value="off" value_type="e_bool"/>
<efx:param name="load_delaym" value="on" value_type="e_bool"/>
<efx:param name="optimization_level" value="NULL" value_type="e_option"/>
<efx:param name="seed" value="1" value_type="e_integer"/>
<efx:param name="placer_effort_level" value="2" value_type="e_option"/>
<efx:param name="max_threads" value="-1" value_type="e_integer"/>
</efx:place_and_route>
<efx:bitstream_generation tool_name="efx_pgm">
<efx:param name="mode" value="active" value_type="e_option" />
<efx:param name="width" value="1" value_type="e_option" />
<efx:param name="enable_roms" value="smart" value_type="e_option" />
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool" />
<efx:param name="io_weak_pullup" value="on" value_type="e_bool" />
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option" />
<efx:param name="bitstream_compression" value="off" value_type="e_bool" />
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool" />
<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option" />
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string" />
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool" />
<efx:param name="cold_boot" value="off" value_type="e_bool" />
<efx:param name="cascade" value="off" value_type="e_option" />
<efx:param name="generate_bit" value="on" value_type="e_bool" />
<efx:param name="generate_bitbin" value="off" value_type="e_bool" />
<efx:param name="generate_hex" value="on" value_type="e_bool" />
<efx:param name="generate_hexbin" value="off" value_type="e_bool" />
<efx:param name="four_byte_addressing" value="off" value_type="e_bool" />
<efx:param name="mode" value="active" value_type="e_option"/>
<efx:param name="width" value="1" value_type="e_option"/>
<efx:param name="enable_roms" value="smart" value_type="e_option"/>
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool"/>
<efx:param name="io_weak_pullup" value="on" value_type="e_bool"/>
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option"/>
<efx:param name="bitstream_compression" value="off" value_type="e_bool"/>
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool"/>
<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option"/>
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string"/>
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool"/>
<efx:param name="cold_boot" value="off" value_type="e_bool"/>
<efx:param name="cascade" value="off" value_type="e_option"/>
<efx:param name="generate_bit" value="on" value_type="e_bool"/>
<efx:param name="generate_bitbin" value="off" value_type="e_bool"/>
<efx:param name="generate_hex" value="on" value_type="e_bool"/>
<efx:param name="generate_hexbin" value="off" value_type="e_bool"/>
<efx:param name="four_byte_addressing" value="off" value_type="e_bool"/>
</efx:bitstream_generation>
<efx:debugger>
<efx:param name="work_dir" value="work_dbg" value_type="e_string" />
<efx:param name="auto_instantiation" value="off" value_type="e_bool" />
<efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string" />
<efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
<efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
<efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string"/>
</efx:debugger>
</efx:project>
</efx:project>