Merge branch '38-increase-cpu-speed' into 'master'
Resolve "Increase CPU Speed" Closes #38 See merge request bslathi19/super6502!33
This commit is contained in:
Byron Lathi
@@ -4,7 +4,7 @@ module sim_top();
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`include "include/super6502_sdram_controller_define.vh"
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logic r_sysclk, r_sdrclk, r_clk_50, r_clk_2;
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logic r_sysclk, r_sdrclk, r_clk_50, r_clk_cpu;
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// clk_100
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initial begin
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@@ -30,14 +30,18 @@ initial begin
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end
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end
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// clk_2
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// clk_cpu
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initial begin
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r_clk_2 <= '1;
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r_clk_cpu <= '1;
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forever begin
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#250 r_clk_2 <= ~r_clk_2;
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#125 r_clk_cpu <= ~r_clk_cpu;
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end
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end
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// initial begin
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// #275000 $finish();
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// end
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initial begin
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$dumpfile("sim_top.vcd");
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$dumpvars(0,sim_top);
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@@ -47,9 +51,9 @@ logic button_reset;
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initial begin
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button_reset <= '0;
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repeat(10) @(r_clk_2);
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repeat(10) @(r_clk_cpu);
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button_reset <= '1;
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repeat(1000000) @(r_clk_2);
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repeat(1000000) @(r_clk_cpu);
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$finish();
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end
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@@ -101,7 +105,7 @@ super6502 u_dut(
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.i_sdrclk(r_sdrclk),
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.i_tACclk(~r_sdrclk),
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.clk_50(r_clk_50),
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.clk_2(r_clk_2),
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.clk_cpu(r_clk_cpu),
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.button_reset(button_reset),
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.cpu_resb(w_cpu_reset),
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.cpu_addr(w_cpu_addr),
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@@ -70,10 +70,11 @@ assign o_sdr_DQM = w_sdr_DQM[0+:2];
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// But basically if we are in access, and cpuclk goes low, go back to wait.
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// If something actually happened, we would be in one of the read/write states.
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enum bit [1:0] {ACCESS, READ_WAIT, WRITE_WAIT, WAIT} state, next_state;
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enum bit [2:0] {ACCESS, PRE_READ, READ_WAIT, PRE_WRITE, WRITE_WAIT, WAIT} state, next_state;
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logic w_read, w_write, w_last;
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logic [23:0] w_addr, r_addr;
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logic [23:0] w_read_addr, w_write_addr;
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logic [23:0] r_read_addr, r_write_addr;
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logic [31:0] w_data_i, w_data_o;
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logic [3:0] w_dm, r_dm;
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@@ -86,25 +87,15 @@ logic [31:0] r_write_data;
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logic [1:0] counter, next_counter;
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always @(posedge i_sysclk) begin
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if (i_arst) begin
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state <= WAIT;
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counter <= '0;
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end else begin
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state <= next_state;
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counter <= next_counter;
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r_write_data <= w_data_i;
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r_addr <= w_addr;
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r_dm <= w_dm;
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end
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if (w_data_valid)
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o_data <= _data;
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end
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logic [7:0] o_data_next;
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logic [23:0] addr_mux_out;
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logic slow_mem;
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logic r_wait;
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logic _r_wait;
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assign o_wait = r_wait & i_cs;
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assign o_wait = (r_wait | slow_mem) & i_cs;
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// we need to assert rdy low until a falling edge if a reset happens
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@@ -126,6 +117,20 @@ always @(posedge i_sysclk or posedge i_arst) begin
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end
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end
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end
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if (i_arst) begin
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state <= WAIT;
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counter <= '0;
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end else begin
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state <= next_state;
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counter <= next_counter;
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r_write_data <= w_data_i;
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r_read_addr <= w_read_addr;
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r_write_addr <= w_write_addr;
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r_dm <= w_dm;
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end
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o_data <= o_data_next;
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end
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//because of timing issues, We really need to trigger
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@@ -157,10 +162,12 @@ end
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always_comb begin
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slow_mem = '0;
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next_state = state;
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next_counter = counter;
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w_addr = '0;
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w_read_addr = '0;
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w_write_addr = '0;
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w_dm = '0;
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w_read = '0;
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w_write = '0;
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@@ -171,65 +178,81 @@ always_comb begin
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unique case (state)
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WAIT: begin
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if (i_cs & i_cpuclk)
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if (i_cs & ~i_cpuclk)
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next_state = ACCESS;
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end
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ACCESS: begin
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// only do something if selected
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if (i_cs) begin
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w_addr = {{i_addr[24:2]}, {1'b0}};; // divide by 2, set last bit to 0
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w_read_addr = {{i_addr[24:2]}, {1'b0}}; // divide by 2, set last bit to 0
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w_write_addr = {{i_addr[24:2]}, {1'b0}}; // divide by 2, set last bit to 0
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addr_mux_out = w_read_addr;
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if (i_rwb) begin //read
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w_read = '1;
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w_last = '1;
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// dm is not needed for reads?
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if (w_rd_ack) next_state = READ_WAIT;
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next_state = PRE_READ;
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end else begin //write
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w_data_i = i_data << (8*i_addr[1:0]);
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//w_data_i = {4{i_data}}; //does anything get through?
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w_dm = ~(4'b1 << i_addr[1:0]);
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if (~i_cpuclk) begin
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w_write = '1;
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w_last = '1;
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next_state = WRITE_WAIT;
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end
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next_state = PRE_WRITE;
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end
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end
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end
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PRE_WRITE: begin
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w_data_i = r_write_data;
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w_write_addr = r_write_addr;
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addr_mux_out = w_write_addr;
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w_dm = r_dm;
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//w_data_i = {4{i_data}}; //does anything get through?
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if (~i_cpuclk) begin
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w_write = '1;
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w_last = '1;
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next_state = WRITE_WAIT;
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end
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end
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WRITE_WAIT: begin
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// stay in this state until write is acknowledged.
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w_write_addr = r_write_addr;
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addr_mux_out = w_write_addr;
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w_write = '1;
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w_last = '1;
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w_data_i = r_write_data;
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w_dm = r_dm;
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w_addr = r_addr;
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if (w_wr_ack) next_state = WAIT;
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end
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PRE_READ: begin
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w_read_addr = r_read_addr;
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addr_mux_out = w_read_addr;
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w_read = '1;
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w_last = '1;
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slow_mem = '1;
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// dm is not needed for reads?
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if (w_rd_ack) next_state = READ_WAIT;
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end
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READ_WAIT: begin
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w_read_addr = r_read_addr;
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addr_mux_out = w_read_addr;
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slow_mem = '1;
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if (w_rd_valid) begin
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w_data_valid = '1;
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_data = w_data_o[8*i_addr[1:0]+:8];
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end
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// you must wait until the next cycle!
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if (~i_cpuclk) begin
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if (w_data_valid) begin
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next_state = WAIT;
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end
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end
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endcase
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end
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//this seems scuffed
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logic [23:0] addr_mux_out;
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always_comb begin
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if (state == ACCESS) begin
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addr_mux_out = w_addr;
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if (w_data_valid) begin
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o_data_next = _data;
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end else begin
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addr_mux_out = r_addr;
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o_data_next = o_data;
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end
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end
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@@ -11,7 +11,7 @@ module super6502
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input button_reset,
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input pll_cpu_locked,
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input clk_50,
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input clk_2,
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input clk_cpu,
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input logic [15:0] cpu_addr,
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output logic [7:0] cpu_data_out,
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output logic [7:0] cpu_data_oe,
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@@ -56,11 +56,11 @@ assign cpu_nmib = '1;
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logic w_wait;
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assign cpu_rdy = ~w_wait;
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assign cpu_phi2 = clk_2;
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assign cpu_phi2 = clk_cpu;
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logic w_sdr_init_done;
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always @(posedge clk_2) begin
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always @(posedge clk_cpu) begin
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if (button_reset == '0) begin
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cpu_resb <= '0;
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end
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@@ -124,12 +124,12 @@ end
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rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom(
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.addr(cpu_addr[11:0]),
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.clk(clk_2),
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.clk(clk_cpu),
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.data(w_rom_data_out)
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);
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leds u_leds(
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.clk(clk_2),
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.clk(clk_cpu),
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.i_data(cpu_data_in),
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.o_data(w_leds_data_out),
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.cs(w_leds_cs),
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@@ -140,7 +140,7 @@ leds u_leds(
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logic w_timer_irqb;
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timer u_timer(
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.clk(clk_2),
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.clk(clk_cpu),
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.reset(~cpu_resb),
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.i_data(cpu_data_in),
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.o_data(w_timer_data_out),
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@@ -151,7 +151,7 @@ timer u_timer(
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);
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multiplier u_multiplier(
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.clk(clk_2),
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.clk(clk_cpu),
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.reset(~cpu_resb),
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.i_data(cpu_data_in),
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.o_data(w_multiplier_data_out),
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@@ -161,7 +161,7 @@ multiplier u_multiplier(
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);
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divider_wrapper u_divider(
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.clk(clk_2),
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.clk(clk_cpu),
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.divclk(clk_50),
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.reset(~cpu_resb),
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.i_data(cpu_data_in),
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@@ -174,7 +174,7 @@ divider_wrapper u_divider(
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logic w_uart_irqb;
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uart_wrapper u_uart(
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.clk(clk_2),
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.clk(clk_cpu),
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.clk_50(clk_50),
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.reset(~cpu_resb),
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.i_data(cpu_data_in),
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@@ -188,7 +188,7 @@ uart_wrapper u_uart(
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);
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spi_controller spi_controller(
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.i_clk(clk_2),
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.i_clk(clk_cpu),
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.i_rst(~cpu_resb),
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.i_cs(w_spi_cs),
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.i_rwb(cpu_rwb),
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@@ -204,7 +204,7 @@ spi_controller spi_controller(
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sdram_adapter u_sdram_adapter(
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.i_cpuclk(clk_2),
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.i_cpuclk(clk_cpu),
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.i_arst(~button_reset),
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.i_sysclk(i_sysclk),
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.i_sdrclk(i_sdrclk),
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@@ -234,7 +234,7 @@ sdram_adapter u_sdram_adapter(
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);
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interrupt_controller u_interrupt_controller(
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.clk(clk_2),
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.clk(clk_cpu),
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.reset(~cpu_resb),
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.i_data(cpu_data_in),
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.o_data(w_irq_data_out),
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@@ -1,105 +1,106 @@
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<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502" description="" last_change_date="Thu Sep 28 2023 09:38:33 PM" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
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<?xml version="1.0" encoding="UTF-8"?>
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<efx:project name="super6502" description="" last_change_date="Sun October 15 2023 13:52:14" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
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<efx:device_info>
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<efx:family name="Trion" />
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<efx:device name="T20F256" />
|
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<efx:timing_model name="C4" />
|
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<efx:family name="Trion"/>
|
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<efx:device name="T20F256"/>
|
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<efx:timing_model name="C4"/>
|
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</efx:device_info>
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<efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008">
|
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<efx:top_module name="super6502" />
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<efx:design_file name="src/super6502.sv" version="default" library="default" />
|
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<efx:design_file name="src/leds.sv" version="default" library="default" />
|
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<efx:design_file name="src/addr_decode.sv" version="default" library="default" />
|
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<efx:design_file name="src/sdram_adapter.sv" version="default" library="default" />
|
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<efx:design_file name="src/timer.sv" version="default" library="default" />
|
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<efx:design_file name="src/interrupt_controller.sv" version="default" library="default" />
|
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<efx:design_file name="src/multiplier.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/divider_wrapper.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/uart_wrapper.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/sd_controller.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/crc7.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/rom.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/spi_controller.sv" version="default" library="default" />
|
||||
<efx:top_vhdl_arch name="" />
|
||||
<efx:top_module name="super6502"/>
|
||||
<efx:design_file name="src/super6502.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/leds.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/addr_decode.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/sdram_adapter.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/timer.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/interrupt_controller.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/multiplier.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/divider_wrapper.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/uart_wrapper.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/sd_controller.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/crc7.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/rom.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/spi_controller.sv" version="default" library="default"/>
|
||||
<efx:top_vhdl_arch name=""/>
|
||||
</efx:design_info>
|
||||
<efx:constraint_info>
|
||||
<efx:sdc_file name="constraints/super6502.pt.sdc" />
|
||||
<efx:inter_file name="" />
|
||||
<efx:sdc_file name="constraints/super6502.pt.sdc"/>
|
||||
<efx:inter_file name=""/>
|
||||
</efx:constraint_info>
|
||||
<efx:sim_info />
|
||||
<efx:misc_info />
|
||||
<efx:sim_info/>
|
||||
<efx:misc_info/>
|
||||
<efx:ip_info>
|
||||
<efx:ip instance_name="sdram_controller" path="ip/sdram_controller/settings.json">
|
||||
<efx:ip_src_file name="sdram_controller.v" />
|
||||
<efx:ip_src_file name="sdram_controller.v"/>
|
||||
</efx:ip>
|
||||
<efx:ip instance_name="divider" path="ip/divider/settings.json">
|
||||
<efx:ip_src_file name="divider.v" />
|
||||
<efx:ip_src_file name="divider.v"/>
|
||||
</efx:ip>
|
||||
<efx:ip instance_name="uart" path="ip/uart/settings.json">
|
||||
<efx:ip_src_file name="uart.v" />
|
||||
<efx:ip_src_file name="uart.v"/>
|
||||
</efx:ip>
|
||||
</efx:ip_info>
|
||||
<efx:synthesis tool_name="efx_map">
|
||||
<efx:param name="work_dir" value="work_syn" value_type="e_string" />
|
||||
<efx:param name="write_efx_verilog" value="on" value_type="e_bool" />
|
||||
<efx:param name="mode" value="speed" value_type="e_option" />
|
||||
<efx:param name="max_ram" value="-1" value_type="e_integer" />
|
||||
<efx:param name="max_mult" value="-1" value_type="e_integer" />
|
||||
<efx:param name="infer-clk-enable" value="3" value_type="e_option" />
|
||||
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option" />
|
||||
<efx:param name="fanout-limit" value="0" value_type="e_integer" />
|
||||
<efx:param name="bram_output_regs_packing" value="1" value_type="e_option" />
|
||||
<efx:param name="retiming" value="1" value_type="e_option" />
|
||||
<efx:param name="seq_opt" value="1" value_type="e_option" />
|
||||
<efx:param name="blast_const_operand_adders" value="1" value_type="e_option" />
|
||||
<efx:param name="operator-sharing" value="0" value_type="e_option" />
|
||||
<efx:param name="optimize-adder-tree" value="0" value_type="e_option" />
|
||||
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option" />
|
||||
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option" />
|
||||
<efx:param name="min-sr-fanout" value="0" value_type="e_option" />
|
||||
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option" />
|
||||
<efx:param name="blackbox-error" value="1" value_type="e_option" />
|
||||
<efx:param name="allow-const-ram-index" value="0" value_type="e_option" />
|
||||
<efx:param name="hdl-compile-unit" value="1" value_type="e_option" />
|
||||
<efx:param name="create-onehot-fsms" value="0" value_type="e_option" />
|
||||
<efx:param name="min-ce-fanout" value="0" value_type="e_integer" />
|
||||
<efx:param name="mult-decomp-retime" value="0" value_type="e_option" />
|
||||
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option" />
|
||||
<efx:param name="include" value="ip/sdram_controller" value_type="e_string" />
|
||||
<efx:param name="include" value="ip/divider" value_type="e_string" />
|
||||
<efx:param name="include" value="ip/uart" value_type="e_string" />
|
||||
<efx:param name="work_dir" value="work_syn" value_type="e_string"/>
|
||||
<efx:param name="write_efx_verilog" value="on" value_type="e_bool"/>
|
||||
<efx:param name="mode" value="speed" value_type="e_option"/>
|
||||
<efx:param name="max_ram" value="-1" value_type="e_integer"/>
|
||||
<efx:param name="max_mult" value="-1" value_type="e_integer"/>
|
||||
<efx:param name="infer-clk-enable" value="3" value_type="e_option"/>
|
||||
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option"/>
|
||||
<efx:param name="fanout-limit" value="0" value_type="e_integer"/>
|
||||
<efx:param name="bram_output_regs_packing" value="1" value_type="e_option"/>
|
||||
<efx:param name="retiming" value="1" value_type="e_option"/>
|
||||
<efx:param name="seq_opt" value="1" value_type="e_option"/>
|
||||
<efx:param name="blast_const_operand_adders" value="1" value_type="e_option"/>
|
||||
<efx:param name="operator-sharing" value="0" value_type="e_option"/>
|
||||
<efx:param name="optimize-adder-tree" value="0" value_type="e_option"/>
|
||||
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option"/>
|
||||
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option"/>
|
||||
<efx:param name="min-sr-fanout" value="0" value_type="e_option"/>
|
||||
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option"/>
|
||||
<efx:param name="blackbox-error" value="1" value_type="e_option"/>
|
||||
<efx:param name="allow-const-ram-index" value="0" value_type="e_option"/>
|
||||
<efx:param name="hdl-compile-unit" value="1" value_type="e_option"/>
|
||||
<efx:param name="create-onehot-fsms" value="0" value_type="e_option"/>
|
||||
<efx:param name="min-ce-fanout" value="0" value_type="e_integer"/>
|
||||
<efx:param name="mult-decomp-retime" value="0" value_type="e_option"/>
|
||||
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option"/>
|
||||
<efx:param name="include" value="ip/sdram_controller" value_type="e_string"/>
|
||||
<efx:param name="include" value="ip/divider" value_type="e_string"/>
|
||||
<efx:param name="include" value="ip/uart" value_type="e_string"/>
|
||||
</efx:synthesis>
|
||||
<efx:place_and_route tool_name="efx_pnr">
|
||||
<efx:param name="work_dir" value="work_pnr" value_type="e_string" />
|
||||
<efx:param name="verbose" value="off" value_type="e_bool" />
|
||||
<efx:param name="load_delaym" value="on" value_type="e_bool" />
|
||||
<efx:param name="optimization_level" value="NULL" value_type="e_option" />
|
||||
<efx:param name="seed" value="1" value_type="e_integer" />
|
||||
<efx:param name="placer_effort_level" value="2" value_type="e_option" />
|
||||
<efx:param name="max_threads" value="-1" value_type="e_integer" />
|
||||
<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
|
||||
<efx:param name="verbose" value="off" value_type="e_bool"/>
|
||||
<efx:param name="load_delaym" value="on" value_type="e_bool"/>
|
||||
<efx:param name="optimization_level" value="NULL" value_type="e_option"/>
|
||||
<efx:param name="seed" value="1" value_type="e_integer"/>
|
||||
<efx:param name="placer_effort_level" value="2" value_type="e_option"/>
|
||||
<efx:param name="max_threads" value="-1" value_type="e_integer"/>
|
||||
</efx:place_and_route>
|
||||
<efx:bitstream_generation tool_name="efx_pgm">
|
||||
<efx:param name="mode" value="active" value_type="e_option" />
|
||||
<efx:param name="width" value="1" value_type="e_option" />
|
||||
<efx:param name="enable_roms" value="smart" value_type="e_option" />
|
||||
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool" />
|
||||
<efx:param name="io_weak_pullup" value="on" value_type="e_bool" />
|
||||
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option" />
|
||||
<efx:param name="bitstream_compression" value="off" value_type="e_bool" />
|
||||
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool" />
|
||||
<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option" />
|
||||
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string" />
|
||||
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool" />
|
||||
<efx:param name="cold_boot" value="off" value_type="e_bool" />
|
||||
<efx:param name="cascade" value="off" value_type="e_option" />
|
||||
<efx:param name="generate_bit" value="on" value_type="e_bool" />
|
||||
<efx:param name="generate_bitbin" value="off" value_type="e_bool" />
|
||||
<efx:param name="generate_hex" value="on" value_type="e_bool" />
|
||||
<efx:param name="generate_hexbin" value="off" value_type="e_bool" />
|
||||
<efx:param name="four_byte_addressing" value="off" value_type="e_bool" />
|
||||
<efx:param name="mode" value="active" value_type="e_option"/>
|
||||
<efx:param name="width" value="1" value_type="e_option"/>
|
||||
<efx:param name="enable_roms" value="smart" value_type="e_option"/>
|
||||
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool"/>
|
||||
<efx:param name="io_weak_pullup" value="on" value_type="e_bool"/>
|
||||
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option"/>
|
||||
<efx:param name="bitstream_compression" value="off" value_type="e_bool"/>
|
||||
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool"/>
|
||||
<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option"/>
|
||||
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string"/>
|
||||
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool"/>
|
||||
<efx:param name="cold_boot" value="off" value_type="e_bool"/>
|
||||
<efx:param name="cascade" value="off" value_type="e_option"/>
|
||||
<efx:param name="generate_bit" value="on" value_type="e_bool"/>
|
||||
<efx:param name="generate_bitbin" value="off" value_type="e_bool"/>
|
||||
<efx:param name="generate_hex" value="on" value_type="e_bool"/>
|
||||
<efx:param name="generate_hexbin" value="off" value_type="e_bool"/>
|
||||
<efx:param name="four_byte_addressing" value="off" value_type="e_bool"/>
|
||||
</efx:bitstream_generation>
|
||||
<efx:debugger>
|
||||
<efx:param name="work_dir" value="work_dbg" value_type="e_string" />
|
||||
<efx:param name="auto_instantiation" value="off" value_type="e_bool" />
|
||||
<efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string" />
|
||||
<efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
|
||||
<efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
|
||||
<efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string"/>
|
||||
</efx:debugger>
|
||||
</efx:project>
|
||||
</efx:project>
|
||||
|
||||
@@ -17,6 +17,6 @@ kernel:
|
||||
|
||||
|
||||
clean:
|
||||
@$(MAKE) -C bootloader --no-print-directory $@
|
||||
@$(MAKE) -C bios --no-print-directory $@
|
||||
@$(MAKE) -C kernel --no-print-directory $@
|
||||
@$(MAKE) -C cc65 --no-print-directory $@
|
||||
@$(MAKE) -C cc65 --no-print-directory $@
|
||||
|
||||
39
sw/test_code/indirect_test/Makefile
Normal file
39
sw/test_code/indirect_test/Makefile
Normal file
@@ -0,0 +1,39 @@
|
||||
CC=../../cc65/bin/cl65
|
||||
LD=../../cc65/bin/cl65
|
||||
CFLAGS=-T -t none -I. --cpu "65C02"
|
||||
LDFLAGS=-C link.ld -m $(NAME).map
|
||||
|
||||
NAME=indirect_test
|
||||
|
||||
BIN=$(NAME).bin
|
||||
HEX=$(NAME).hex
|
||||
|
||||
LISTS=lists
|
||||
|
||||
SRCS=$(wildcard *.s) $(wildcard *.c)
|
||||
SRCS+=$(wildcard **/*.s) $(wildcard **/*.c)
|
||||
OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS)))
|
||||
OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
|
||||
|
||||
# Make sure the kernel linked to correct address, no relocation!
|
||||
all: $(HEX)
|
||||
|
||||
$(HEX): $(BIN)
|
||||
objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX)
|
||||
|
||||
$(BIN): $(OBJS)
|
||||
$(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@
|
||||
|
||||
%.o: %.c $(LISTS)
|
||||
$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
|
||||
|
||||
%.o: %.s $(LISTS)
|
||||
$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
|
||||
|
||||
$(LISTS):
|
||||
mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS))))
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map
|
||||
|
||||
35
sw/test_code/indirect_test/link.ld
Normal file
35
sw/test_code/indirect_test/link.ld
Normal file
@@ -0,0 +1,35 @@
|
||||
MEMORY
|
||||
{
|
||||
ZP: start = $0, size = $100, type = rw, define = yes;
|
||||
SDRAM: start = $9200, size = $4d00, type = rw, define = yes;
|
||||
ROM: start = $F000, size = $1000, file = %O;
|
||||
}
|
||||
|
||||
SEGMENTS {
|
||||
ZEROPAGE: load = ZP, type = zp, define = yes;
|
||||
DATA: load = ROM, type = rw, define = yes, run = SDRAM;
|
||||
BSS: load = SDRAM, type = bss, define = yes;
|
||||
HEAP: load = SDRAM, type = bss, optional = yes;
|
||||
STARTUP: load = ROM, type = ro;
|
||||
ONCE: load = ROM, type = ro, optional = yes;
|
||||
CODE: load = ROM, type = ro;
|
||||
RODATA: load = ROM, type = ro;
|
||||
VECTORS: load = ROM, type = ro, start = $FFFA;
|
||||
}
|
||||
|
||||
FEATURES {
|
||||
CONDES: segment = STARTUP,
|
||||
type = constructor,
|
||||
label = __CONSTRUCTOR_TABLE__,
|
||||
count = __CONSTRUCTOR_COUNT__;
|
||||
CONDES: segment = STARTUP,
|
||||
type = destructor,
|
||||
label = __DESTRUCTOR_TABLE__,
|
||||
count = __DESTRUCTOR_COUNT__;
|
||||
}
|
||||
|
||||
SYMBOLS {
|
||||
# Define the stack size for the application
|
||||
__STACKSIZE__: value = $0200, type = weak;
|
||||
__STACKSTART__: type = weak, value = $0800; # 2k stack
|
||||
}
|
||||
20
sw/test_code/indirect_test/main.s
Normal file
20
sw/test_code/indirect_test/main.s
Normal file
@@ -0,0 +1,20 @@
|
||||
.export _init, _nmi_int, _irq_int
|
||||
|
||||
.code
|
||||
|
||||
_nmi_int:
|
||||
_irq_int:
|
||||
|
||||
_init:
|
||||
ldx #$ff
|
||||
txs
|
||||
|
||||
lda #$aa
|
||||
sta $01
|
||||
lda #$bb
|
||||
sta $00
|
||||
ldy #$1
|
||||
lda #$cc
|
||||
sta ($00),y
|
||||
|
||||
@end: bra @end
|
||||
14
sw/test_code/indirect_test/vectors.s
Normal file
14
sw/test_code/indirect_test/vectors.s
Normal file
@@ -0,0 +1,14 @@
|
||||
; ---------------------------------------------------------------------------
|
||||
; vectors.s
|
||||
; ---------------------------------------------------------------------------
|
||||
;
|
||||
; Defines the interrupt vector table.
|
||||
|
||||
.import _init
|
||||
.import _nmi_int, _irq_int
|
||||
|
||||
.segment "VECTORS"
|
||||
|
||||
.addr _nmi_int ; NMI vector
|
||||
.addr _init ; Reset vector
|
||||
.addr _irq_int ; IRQ/BRK vector
|
||||
39
sw/test_code/jsr_test/Makefile
Normal file
39
sw/test_code/jsr_test/Makefile
Normal file
@@ -0,0 +1,39 @@
|
||||
CC=../../cc65/bin/cl65
|
||||
LD=../../cc65/bin/cl65
|
||||
CFLAGS=-T -t none -I. --cpu "65C02"
|
||||
LDFLAGS=-C link.ld -m $(NAME).map
|
||||
|
||||
NAME=jsr_test
|
||||
|
||||
BIN=$(NAME).bin
|
||||
HEX=$(NAME).hex
|
||||
|
||||
LISTS=lists
|
||||
|
||||
SRCS=$(wildcard *.s) $(wildcard *.c)
|
||||
SRCS+=$(wildcard **/*.s) $(wildcard **/*.c)
|
||||
OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS)))
|
||||
OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
|
||||
|
||||
# Make sure the kernel linked to correct address, no relocation!
|
||||
all: $(HEX)
|
||||
|
||||
$(HEX): $(BIN)
|
||||
objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX)
|
||||
|
||||
$(BIN): $(OBJS)
|
||||
$(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@
|
||||
|
||||
%.o: %.c $(LISTS)
|
||||
$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
|
||||
|
||||
%.o: %.s $(LISTS)
|
||||
$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
|
||||
|
||||
$(LISTS):
|
||||
mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS))))
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map
|
||||
|
||||
35
sw/test_code/jsr_test/link.ld
Normal file
35
sw/test_code/jsr_test/link.ld
Normal file
@@ -0,0 +1,35 @@
|
||||
MEMORY
|
||||
{
|
||||
ZP: start = $0, size = $100, type = rw, define = yes;
|
||||
SDRAM: start = $9200, size = $4d00, type = rw, define = yes;
|
||||
ROM: start = $F000, size = $1000, file = %O;
|
||||
}
|
||||
|
||||
SEGMENTS {
|
||||
ZEROPAGE: load = ZP, type = zp, define = yes;
|
||||
DATA: load = ROM, type = rw, define = yes, run = SDRAM;
|
||||
BSS: load = SDRAM, type = bss, define = yes;
|
||||
HEAP: load = SDRAM, type = bss, optional = yes;
|
||||
STARTUP: load = ROM, type = ro;
|
||||
ONCE: load = ROM, type = ro, optional = yes;
|
||||
CODE: load = ROM, type = ro;
|
||||
RODATA: load = ROM, type = ro;
|
||||
VECTORS: load = ROM, type = ro, start = $FFFA;
|
||||
}
|
||||
|
||||
FEATURES {
|
||||
CONDES: segment = STARTUP,
|
||||
type = constructor,
|
||||
label = __CONSTRUCTOR_TABLE__,
|
||||
count = __CONSTRUCTOR_COUNT__;
|
||||
CONDES: segment = STARTUP,
|
||||
type = destructor,
|
||||
label = __DESTRUCTOR_TABLE__,
|
||||
count = __DESTRUCTOR_COUNT__;
|
||||
}
|
||||
|
||||
SYMBOLS {
|
||||
# Define the stack size for the application
|
||||
__STACKSIZE__: value = $0200, type = weak;
|
||||
__STACKSTART__: type = weak, value = $0800; # 2k stack
|
||||
}
|
||||
23
sw/test_code/jsr_test/main.s
Normal file
23
sw/test_code/jsr_test/main.s
Normal file
@@ -0,0 +1,23 @@
|
||||
.export _init, _nmi_int, _irq_int
|
||||
|
||||
.code
|
||||
|
||||
_nmi_int:
|
||||
_irq_int:
|
||||
|
||||
_init:
|
||||
ldx #$ff
|
||||
txs
|
||||
lda #$00
|
||||
jsr subroutine
|
||||
sta $00
|
||||
@1: bra @1
|
||||
|
||||
subroutine:
|
||||
inc
|
||||
jsr suborutine2
|
||||
rts
|
||||
|
||||
suborutine2:
|
||||
inc
|
||||
rts
|
||||
14
sw/test_code/jsr_test/vectors.s
Normal file
14
sw/test_code/jsr_test/vectors.s
Normal file
@@ -0,0 +1,14 @@
|
||||
; ---------------------------------------------------------------------------
|
||||
; vectors.s
|
||||
; ---------------------------------------------------------------------------
|
||||
;
|
||||
; Defines the interrupt vector table.
|
||||
|
||||
.import _init
|
||||
.import _nmi_int, _irq_int
|
||||
|
||||
.segment "VECTORS"
|
||||
|
||||
.addr _nmi_int ; NMI vector
|
||||
.addr _init ; Reset vector
|
||||
.addr _irq_int ; IRQ/BRK vector
|
||||
Reference in New Issue
Block a user