bslathi19/super6502
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge from master

Browse Source
This commit is contained in:
Byron Lathi
2023-10-15 18:58:25 -07:00
parent 76aea3180a fd4dbfaf81
commit 155e89240a
48 changed files with 2545 additions and 705 deletions
Download Patch File Download Diff File Expand all files Collapse all files

118
.gitlab-ci.yml Normal file
View File

@@ -0,0 +1,118 @@
# This file is a template, and might need editing before it works on your project.
# This is a sample GitLab CI/CD configuration file that should run without any modifications.
# It demonstrates a basic 3 stage CI/CD pipeline. Instead of real tests or scripts,
# it uses echo commands to simulate the pipeline execution.
#
# A pipeline is composed of independent jobs that run scripts, grouped into stages.
# Stages run in sequential order, but jobs within stages run in parallel.
#
# For more information, see: https://docs.gitlab.com/ee/ci/yaml/index.html#stages
#
# You can copy and paste this template into a new `.gitlab-ci.yml` file.
# You should not add this template to an existing `.gitlab-ci.yml` file by using the `include:` keyword.
#
# To contribute improvements to CI/CD templates, please follow the Development guide at:
# https://docs.gitlab.com/ee/development/cicd/templates.html
# This specific template is located at:
# https://gitlab.com/gitlab-org/gitlab/-/blob/master/lib/gitlab/ci/templates/Getting-Started.gitlab-ci.yml
variables:
GIT_SUBMODULE_STRATEGY: recursive
stages: # List of stages for jobs, and their order of execution
- toolchain
- build
- simulate
build toolchain:
tags:
- linux
stage: toolchain
script:
- source init_env.sh
- cd sw/cc65
- make -j
artifacts:
paths:
- sw/cc65/bin
- sw/cc65/lib
build fpga: # This job runs in the build stage, which runs first.
tags:
- efinity
- linux
stage: build
script:
- source init_env.sh
- cd hw/efinix_fpga
- make
build sim:
tags:
- iverilog
- linux
stage: build
artifacts:
paths:
- hw/efinix_fpga/simulation/sim_top
- hw/efinix_fpga/simulation/init_hex.mem
script:
- source init_env.sh
- cd hw/efinix_fpga/simulation
- make sim_top
dependencies:
- build toolchain
build bios:
tags:
- linux
stage: build
script:
- source init_env.sh
- cd sw/
- make bios
dependencies:
- build toolchain
build kernel:
tags:
- linux
stage: build
script:
- source init_env.sh
- cd sw/
- make kernel
dependencies:
- build toolchain
run sim:
tags:
- linux
- iverilog
stage: simulate
artifacts:
paths:
- hw/efinix_fpga/simulation/sim_top.vcd
script:
- source init_env.sh
- cd hw/efinix_fpga/simulation
- make sim
dependencies:
- build sim
full sim:
tags:
- linux
- iverilog
stage: simulate
artifacts:
paths:
- hw/efinix_fpga/simulation/sim_top.vcd
script:
- source init_env.sh
- cd hw/efinix_fpga/simulation
- make clean
- TEST_PROGRAM=$REPO_TOP/sw/bios/bios.hex TEST_FOLDER=$REPO_TOP/sw/bios make full_sim
dependencies:
- build toolchain

6
.gitmodules vendored
View File

@@ -1,3 +1,9 @@
[submodule "sw/cc65"]
path = sw/cc65
url = https://git.byronlathi.com/bslathi19/cc65
[submodule "hw/efinix_fpga/simulation/src/verilog-6502"]
path = hw/efinix_fpga/simulation/src/verilog-6502
url = https://git.byronlathi.com/bslathi19/verilog-6502
[submodule "hw/efinix_fpga/simulation/src/verilog-sd-emulator"]
path = hw/efinix_fpga/simulation/src/verilog-sd-emulator
url = https://git.byronlathi.com/bslathi19/verilog-sd-emulator

426
hw/efinix_fpga/init_hex.mem
View File

@@ -1,9 +1,9 @@
@00000000
00 80 4C 00 00 8D 13 92 8E 14 92 8D 1A 92 8E 1B
92 88 B9 FF FF 8D 24 92 88 B9 FF FF 8D 23 92 8C
26 92 20 FF FF A0 FF D0 E8 60 00 00 CC FD 00 00
00 00 A2 FF 9A D8 A9 00 85 04 A9 DF 85 05 20 44
FE 20 B9 FA 20 52 F0 58 20 69 F2 6C FC FF 20 AD
26 92 20 FF FF A0 FF D0 E8 60 00 00 4B FD 00 00
00 00 A2 FF 9A D8 A9 00 85 04 A9 DF 85 05 20 C3
FD 20 38 FA 20 52 F0 58 20 69 F2 6C FC FF 20 2C
FA 00 A0 00 F0 07 A9 52 A2 F0 4C 05 92 60 AD FF
EF A2 00 60 8D FF EF 60 20 4F F2 C9 0A D0 05 A9
0D 20 4F F2 60 DA 5A A8 B2 04 AA A9 1B 20 4F F2
@@ -13,19 +13,19 @@ A9 63 20 4F F2 68 60 40 DA BA 48 E8 E8 BD 00 01
29 10 D0 06 68 FA 20 68 F2 40 68 FA 7C BF F0 C5
F0 C9 F0 CA F0 20 9A F0 40 40 20 68 F0 40 48 A0
04 B1 04 09 40 20 3F F2 88 B1 04 20 3F F2 88 10
F8 68 09 01 20 3F F2 20 A9 FB 60 A2 08 A9 FF 20
F8 68 09 01 20 3F F2 20 28 FB 60 A2 08 A9 FF 20
3F F2 C9 FF D0 03 CA D0 F4 60 85 0C 86 0D 20 EB
F0 92 0C A9 FF 20 3F F2 A0 01 91 0C 20 96 FB 60
AA 20 20 FD A9 FF 20 3F F2 92 0C E6 0C D0 02 E6
F0 92 0C A9 FF 20 3F F2 A0 01 91 0C 20 15 FB 60
AA 20 9F FC A9 FF 20 3F F2 92 0C E6 0C D0 02 E6
0D CA D0 F0 60 85 0C 86 0D 20 EB F0 C9 02 B0 12
E6 0C D0 02 E6 0C A5 0C A6 0D 20 4D FD A9 04 20
E6 0C D0 02 E6 0C A5 0C A6 0D 20 CC FC A9 04 20
10 F1 60 48 A9 FF 20 3F F2 A9 00 20 33 F2 A9 FF
20 3F F2 68 20 CE F0 20 EB F0 A8 A9 FF 20 3F F2
A9 00 20 39 F2 A9 FF 20 3F F2 98 A2 00 60 A9 00
20 39 F2 20 8B F1 A9 FF 20 3F F2 A9 00 20 39 F2
A2 50 A9 FF 20 3F F2 CA D0 F8 60 A2 01 A9 C8 3A
D0 FD CA D0 F8 60 85 0E 86 0F A9 FF 92 0E 20 20
FD A5 04 85 10 A5 05 85 11 20 51 FB A0 00 B1 10
D0 FD CA D0 F8 60 85 0E 86 0F A9 FF 92 0E 20 9F
FC A5 04 85 10 A5 05 85 11 20 D0 FA A0 00 B1 10
91 04 C8 B1 10 91 04 C8 B1 10 91 04 C8 B1 10 91
04 A9 FF 20 3F F2 A9 00 20 33 F2 A9 FF 20 3F F2
A9 11 A0 04 91 04 A9 00 20 CE F0 20 EB F0 C9 FF
@@ -37,211 +37,211 @@ EB A9 FF 20 3F F2 A9 FF 20 3F F2 A5 15 92 0E A5
F2 68 60 A9 01 8D DB EF 60 9C DB EF 60 A9 00 8D
DA EF AD DB EF 30 FB AD D9 EF 60 8D E6 EF 60 48
8D E6 EF AD E7 EF 89 02 D0 F9 68 60 AD E6 EF A2
00 60 AD E7 EF A2 00 60 60 20 74 FB A2 00 86 06
86 07 A9 00 20 0B FC 20 5A FB A9 89 A2 FE 20 1A
FB 20 3A F3 C9 00 20 B8 FC D0 03 4C 98 F2 A9 81
A2 FE 20 1A FB 4C 2E F3 A9 77 A2 FE 20 1A FB A0
05 20 C7 FB 20 0B FC AD 00 92 AE 01 92 20 4D FD
A9 0C 20 D8 FB 20 96 F1 A0 07 91 04 A0 07 A2 00
B1 04 C9 00 20 BE FC D0 03 4C DC F2 A0 06 A2 00
B1 04 C9 FE 20 BE FC F0 03 4C E5 F2 A2 00 A9 00
00 60 AD E7 EF A2 00 60 60 20 F3 FA A2 00 86 06
86 07 A9 00 20 8A FB 20 D9 FA A9 05 A2 FE 20 99
FA 20 3A F3 C9 00 20 37 FC D0 03 4C 98 F2 A9 FE
A2 FD 20 99 FA 4C 2E F3 A9 F5 A2 FD 20 99 FA A0
05 20 46 FB 20 8A FB AD 00 92 AE 01 92 20 CC FC
A9 0C 20 57 FB 20 96 F1 A0 07 91 04 A0 07 A2 00
B1 04 C9 00 20 3D FC D0 03 4C DC F2 A0 06 A2 00
B1 04 C9 FE 20 3D FC F0 03 4C E5 F2 A2 00 A9 00
D0 03 4C E9 F2 A2 00 A9 01 D0 03 4C FA F2 AD 00
92 AE 01 92 20 3C F6 4C 2B F3 A0 06 A2 00 B1 04
A2 00 29 F0 20 9F FA D0 03 4C 16 F3 A9 81 A2 FE
20 1A FB 4C 2B F3 A9 67 A2 FE 20 4D FD A0 08 A2
00 B1 04 20 4D FD A0 04 20 E6 FA 6C 00 92 4C 31
F3 4C 31 F3 A0 0C 20 85 FA 60 20 81 FB A9 00 20
37 FD 20 6E F1 4C 71 F3 A0 00 A2 00 18 A9 01 71
04 91 04 A0 00 A2 00 B1 04 C9 FF 20 BE FC D0 03
4C 71 F3 A9 AB A2 FE 20 1A FB A2 00 A9 01 4C A8
F4 20 AC F4 A0 01 91 04 C9 01 20 B8 FC D0 C9 A2
00 A9 00 A0 06 20 65 FD A0 07 20 BE FB E0 03 D0
02 C9 E8 20 D7 FC F0 03 4C 9E F3 4C AA F3 A0 06
A2 00 A9 01 20 75 FA 4C 88 F3 A9 01 20 D8 FB 20
C9 F4 A0 01 A2 00 B1 04 C9 01 20 B8 FC D0 03 4C
D0 F3 A9 A1 A2 FE 20 1A FB A2 00 A9 01 4C A8 F4
A0 05 A2 00 B1 04 C9 AA 20 B8 FC D0 03 4C E7 F3
A2 00 A9 01 4C A8 F4 A2 00 A9 00 A0 00 91 04 A0
00 A2 00 B1 04 C9 FF 20 BE FC D0 03 4C 0D F4 A9
91 A2 FE 20 1A FB A2 00 A9 01 4C A8 F4 20 EB F5
A0 01 91 04 A0 01 A2 00 B1 04 C9 02 20 D7 FC D0
03 4C 2B F4 20 08 F6 A0 01 91 04 A2 00 A9 00 A0
06 20 65 FD A0 07 20 BE FB E0 03 D0 02 C9 E8 20
D7 FC F0 03 4C 4A F4 4C 56 F4 A0 06 A2 00 A9 01
20 75 FA 4C 34 F4 A0 00 A2 00 18 A9 01 71 04 91
04 A0 01 A2 00 B1 04 C9 00 20 B8 FC D0 81 A2 00
A9 00 A0 06 20 65 FD A0 07 20 BE FB E0 03 D0 02
C9 E8 20 D7 FC F0 03 4C 8D F4 4C 99 F4 A0 06 A2
00 A9 01 20 75 FA 4C 77 F4 A9 01 20 D8 FB 20 71
F5 A2 00 A9 00 4C A8 F4 20 AE FB 60 A2 00 A9 00
20 37 FD A2 00 86 06 86 07 A9 00 20 0B FC A2 00
A9 94 20 43 F1 4C C8 F4 60 20 4D FD A2 00 A9 FF
20 3F F2 A2 00 A9 00 20 33 F2 A2 00 A9 FF 20 3F
F2 A2 00 A9 08 20 37 FD A2 01 A9 00 85 06 A9 00
85 07 A9 AA 20 0B FC A2 00 A9 86 20 CE F0 A0 01
20 BE FB 20 25 F1 A2 00 A9 FF 20 3F F2 A2 00 A9
00 20 39 F2 A2 00 A9 FF 20 3F F2 20 96 FB 60 20
4D FD A2 00 A9 FF 20 3F F2 A2 00 A9 00 20 33 F2
A2 00 A9 FF 20 3F F2 A2 00 A9 0D 20 37 FD A2 00
86 06 86 07 A9 00 20 0B FC A2 00 A9 00 20 CE F0
A0 01 20 BE FB 20 FA F0 A2 00 A9 FF 20 3F F2 A2
00 A9 00 20 39 F2 A2 00 A9 FF 20 3F F2 20 96 FB
60 20 4D FD 20 51 FB A2 00 A9 FF 20 3F F2 A2 00
A9 00 20 33 F2 A2 00 A9 FF 20 3F F2 A0 00 91 04
A0 00 A2 00 B1 04 C9 FF 20 B8 FC D0 03 4C B1 F5
4C A3 F5 A2 00 A9 FF 20 3F F2 C9 FF 20 B8 FC D0
F2 A2 00 A9 3A 20 37 FD A2 00 86 06 86 07 A9 00
20 0B FC A2 00 A9 00 20 CE F0 A0 02 20 BE FB 20
25 F1 A2 00 A9 FF 20 3F F2 A2 00 A9 00 20 39 F2
A2 00 A9 FF 20 3F F2 20 A4 FB 60 A2 00 A9 37 20
37 FD A2 00 86 06 86 07 A9 00 20 0B FC A2 00 A9
00 20 43 F1 4C 07 F6 60 A2 00 A9 29 20 37 FD A2
00 86 06 A9 40 85 07 A9 00 20 0B FC A2 00 A9 00
20 43 F1 4C 26 F6 60 20 4D FD 20 74 FB A0 03 A2
00 B1 04 4C 36 F6 A0 0E 20 85 FA 60 20 4D FD A9
00 20 37 FD 20 5A FB A2 00 A9 00 A0 00 20 65 FD
A0 01 20 BE FB E0 02 20 D7 FC F0 03 4C 62 F6 4C
C4 F6 A9 B5 A2 FE 20 4D FD A0 06 20 BE FB A0 00
20 B3 FB 20 4D FD A0 07 A2 00 A9 01 20 75 FA A0
04 20 E6 FA A0 02 A2 00 B1 04 C9 1F 20 BE FC D0
03 4C A6 F6 A9 B9 A2 FE 20 1A FB A2 00 A9 00 A0
02 91 04 4C B8 F6 A2 00 A9 20 20 68 F0 A0 02 A2
00 18 A9 01 71 04 91 04 A0 00 A2 00 A9 01 20 75
FA 4C 50 F6 A9 B9 A2 FE 20 1A FB 20 A9 FB 60 A0
00 B1 1A E6 1A D0 02 E6 1B 60 AD 4A 92 8D 45 92
20 7B F7 A9 45 A2 92 20 4D FD 20 2E FD 4C 02 92
A5 18 38 E9 02 85 18 B0 02 C6 19 60 AD 4F 92 D0
11 20 19 F7 4C 98 FA AD 4F 92 D0 06 20 19 F7 4C
92 FA 20 19 F7 85 06 86 07 20 F0 F6 A0 01 B1 18
AA 88 B1 18 60 A0 00 84 0C 84 0D B1 1A 38 E9 30
90 2C C9 0A B0 28 20 D3 F6 48 A5 0C A6 0D 06 0C
26 0D 06 0C 26 0D 65 0C 85 0C 8A 65 0D 85 0D 06
0C 26 0D 68 65 0C 85 0C 90 D1 E6 0D B0 CD A5 0C
A6 0D 60 AC 51 92 EE 51 92 99 52 92 60 A9 52 A2
92 18 6D 51 92 90 01 E8 4C 4D FD A5 1C A6 1D 4C
4D FD 20 DA F6 EE 4B 92 D0 F8 EE 4C 92 D0 F3 60
20 7B F7 AD 66 92 AE 67 92 20 4D FD AD 68 92 AE
69 92 20 4D FD 4C 02 92 84 0C 20 0B FC 20 6D F7
A5 0C 4C 3B FC 84 0C 20 0B FC 20 6D F7 A5 0C 4C
7C FC 48 A0 05 B9 18 00 99 3F 92 88 10 F7 68 85
18 86 19 20 8E FB 85 1A 86 1B 20 8E FB 85 1C 86
1D A9 00 A8 91 1C C8 91 1C C8 B1 1C 8D 03 92 C8
B1 1C 8D 04 92 A5 1A 85 0C A5 1B 85 0D A0 00 B1
1A F0 0B C9 25 F0 07 C8 D0 F5 E6 1B D0 F1 98 18
65 1A 85 1A 90 02 E6 1B 38 E5 0C 85 0E A5 1B E5
0D 85 0F 05 0E F0 25 20 74 FB A0 05 A5 1D 91 04
88 A5 1C 91 04 88 A5 0D 91 04 88 A5 0C 91 04 88
A5 0F 91 04 88 A5 0E 91 04 20 02 92 20 CF F6 AA
D0 0B A2 05 BD 3F 92 95 18 CA 10 F8 60 C9 25 D0
09 B1 1A C9 25 D0 09 20 D3 F6 20 DD F6 4C F5 F7
A9 00 A2 0B 9D 46 92 CA 10 FA B1 1A C9 2D D0 05
8E 46 92 F0 19 C9 2B D0 05 8E 47 92 F0 10 C9 20
D0 05 8E 48 92 F0 07 C9 23 D0 09 8E 49 92 20 D3
F6 4C 7A F8 A2 20 C9 30 D0 06 AA 20 D3 F6 B1 1A
8E 4A 92 C9 2A D0 09 20 D3 F6 20 19 F7 4C C3 F8
20 25 F7 8D 4B 92 8E 4C 92 8C 4D 92 8C 4E 92 B1
1A C9 2E D0 1B 20 D3 F6 B1 1A C9 2A D0 09 20 D3
F6 20 19 F7 4C EA F8 20 25 F7 8D 4D 92 8E 4E 92
B1 1A C9 7A F0 19 C9 68 F0 15 C9 74 F0 11 C9 6A
F0 08 C9 4C F0 04 C9 6C D0 0B A9 FF 8D 4F 92 20
D3 F6 4C F0 F8 8C 51 92 A2 52 8E 66 92 A2 92 8E
67 92 20 D3 F6 C9 63 D0 0D 20 19 F7 8D 52 92 A2
00 A9 01 4C 1C FA C9 64 F0 04 C9 69 D0 2D A2 00
AD 48 92 F0 02 A2 20 AD 47 92 F0 02 A2 2B 8E 50
92 20 07 F7 A4 07 30 0B AC 50 92 F0 06 8C 52 92
EE 51 92 A0 0A 20 A8 F7 4C 13 FA C9 6E D0 15 20
19 F7 85 0C 86 0D A0 00 B1 1C 91 0C C8 B1 1C 91
0C 4C F5 F7 C9 6F D0 27 20 07 F7 AC 49 92 F0 17
48 86 14 05 14 05 06 05 07 0D 4D 92 0D 4E 92 F0
06 A9 30 20 63 F7 68 A0 08 20 A8 F7 4C 13 FA C9
70 D0 0D A2 00 8E 4F 92 E8 8E 49 92 A9 78 D0 27
C9 73 D0 0C 20 19 F7 8D 66 92 8E 67 92 4C 13 FA
C9 75 D0 0B 20 FC F6 A0 0A 20 B5 F7 4C 13 FA C9
78 F0 04 C9 58 D0 29 48 AD 49 92 F0 0A A9 30 20
63 F7 A9 58 20 63 F7 20 FC F6 A0 10 20 B5 F7 68
C9 78 D0 09 AD 66 92 AE 67 92 20 A5 FD 4C 13 FA
4C F5 F7 AD 66 92 AE 67 92 20 8F FD 8D 68 92 8E
69 92 AD 4D 92 0D 4E 92 F0 15 AE 4D 92 EC 68 92
AD 4E 92 A8 ED 69 92 B0 06 8E 68 92 8C 69 92 38
AD 4B 92 ED 68 92 AA AD 4C 92 ED 69 92 B0 03 A9
00 AA 49 FF 8D 4C 92 8A 49 FF 8D 4B 92 AD 46 92
D0 03 20 85 F7 20 90 F7 AD 46 92 F0 03 20 85 F7
4C F5 F7 A0 00 18 71 04 91 04 48 C8 8A 71 04 91
04 AA 68 60 C8 48 18 98 65 04 85 04 90 02 E6 05
68 60 A0 FF E0 80 B0 02 A0 00 84 06 84 07 60 E0
00 D0 06 AA D0 03 A9 01 60 A2 00 8A 60 A0 00 F0
07 A9 52 A2 F0 4C 05 92 60 A9 00 85 0C A9 F0 85
0D A9 00 85 0E A9 92 85 0F A2 CD A9 FF 85 14 A0
00 E8 F0 0D B1 0C 91 0E C8 D0 F6 E6 0D E6 0F D0
F0 E6 14 D0 EF 60 8C 6A 92 88 88 98 18 65 04 85
0C A6 05 90 01 E8 86 0D A0 01 B1 0C AA 88 B1 0C
20 4D FD A5 0C A6 0D 20 14 FE AC 6A 92 4C 85 FA
85 0C 86 0D 20 75 F0 4C 1E FB 85 0C 86 0D A0 00
B1 0C F0 0E C8 84 14 20 68 F0 A4 14 D0 F2 E6 0D
D0 EE 60 E0 00 D0 15 4A AA BD E3 FE 90 05 4A 4A
4A 4A 18 29 0F AA BD D8 FE A2 00 60 38 A9 00 AA
60 A4 04 D0 02 C6 05 C6 04 60 A5 04 38 E9 02 85
04 90 01 60 C6 05 60 A5 04 38 E9 04 85 04 90 01
60 C6 05 60 A5 04 38 E9 06 85 04 90 01 60 C6 05
60 A5 04 38 E9 07 85 04 90 01 60 C6 05 60 A0 01
B1 04 AA 88 B1 04 E6 04 F0 05 E6 04 F0 03 60 E6
04 E6 05 60 A0 03 4C 85 FA A0 05 4C 85 FA A0 08
4C 85 FA 85 0C 86 0D A2 00 B1 0C 60 A0 01 B1 04
AA 88 B1 04 60 A0 03 B1 04 85 07 88 B1 04 85 06
88 B1 04 AA 88 B1 04 60 A2 00 18 65 04 48 8A 65
05 AA 68 60 18 49 FF 69 01 48 8A 49 FF 69 00 AA
A5 06 49 FF 69 00 85 06 A5 07 49 FF 69 00 85 07
68 60 A9 00 AA A0 00 84 06 84 07 48 20 67 FB A0
03 A5 07 91 04 88 A5 06 91 04 88 8A 91 04 68 88
91 04 60 85 14 20 8E FB 85 0E 86 0F 85 10 86 11
20 20 FD 20 8E FB 85 06 86 07 60 20 23 FC A6 07
A4 14 C0 0A D0 39 A5 06 05 0D 05 0C D0 11 E0 80
D0 0D A0 0B B9 CC FE 91 0E 88 10 F8 4C B3 FC 8A
10 1D A9 2D A0 00 91 0E E6 0E D0 02 E6 0F A5 0C
A6 0D 20 E4 FB 85 0C 86 0D 4C 7F FC 20 23 FC A9
00 48 A0 20 A9 00 06 0C 26 0D 26 06 26 07 2A C5
14 90 04 E5 14 E6 0C 88 D0 EC A8 B9 BC FE 48 A5
0C 05 0D 05 06 05 07 D0 D9 A0 00 68 91 0E F0 03
C8 D0 F8 A5 10 A6 11 60 D0 06 A2 00 8A 60 D0 FA
A2 00 A9 01 60 F0 F9 30 F7 A2 00 8A 60 F0 02 10
EF A2 00 8A 60 F0 E9 90 E7 A2 00 8A 60 F0 DB A2
00 8A 2A 60 20 0D FD A6 11 F0 13 B1 0C 91 0E C8
B1 0C 91 0E C8 D0 F4 E6 0D E6 0F CA D0 ED A6 10
F0 08 B1 0C 91 0E C8 CA D0 F8 4C 8E FB 85 10 86
11 20 20 FD C8 B1 04 AA 86 0F 88 B1 04 85 0E 60
A0 01 B1 04 85 0D 88 B1 04 85 0C 4C 96 FB A9 01
4C 4B FD A0 00 B1 04 A4 04 F0 07 C6 04 A0 00 91
04 60 C6 05 C6 04 91 04 60 A9 00 A2 00 48 A5 04
38 E9 02 85 04 B0 02 C6 05 A0 01 8A 91 04 68 88
91 04 60 A0 00 91 04 C8 48 8A 91 04 68 60 85 0E
86 0F 20 20 FD B1 0C D1 0E D0 0C AA F0 10 C8 D0
F4 E6 0D E6 0F D0 EE B0 03 A2 FF 60 A2 01 60 85
0E 86 0F A2 00 A0 00 B1 0E F0 08 C8 D0 F9 E6 0F
E8 D0 F4 98 60 85 0C 86 0D 85 0E 86 0F A0 00 B1
0C F0 14 20 37 FB 29 02 F0 06 B1 0C 69 20 91 0C
C8 D0 EC E6 0D D0 E8 A5 0E A6 0F 60 20 8E FB 85
0E 86 0F E8 8E 31 92 AA E8 8E 30 92 20 20 FD 20
8E FB 85 10 86 11 A0 00 84 14 B1 10 18 65 0E 91
10 C8 B1 10 65 0F 91 10 CE 30 92 F0 11 A4 14 B1
0C C8 D0 02 E6 0D 84 14 20 68 F0 4C F8 FD CE 31
92 D0 EA 60 85 0C 86 0D A9 00 8D 2A 92 8D 2B 92
A0 01 B1 04 AA 88 B1 04 20 4D FD A0 02 A9 2A 91
04 C8 A9 92 91 04 A5 0C A6 0D 20 C2 F7 AD 2A 92
AE 2B 92 60 A9 32 85 0C A9 92 85 0D A9 00 A8 A2
00 F0 0A 91 0C C8 D0 FB E6 0D CA D0 F6 C0 39 F0
05 91 0C C8 D0 F7 60 62 61 64 20 74 6F 6B 65 6E
3A 20 25 78 0D 0A 00 53 75 63 63 65 73 73 0D 0A
00 45 72 72 6F 72 0D 0A 00 53 74 61 72 74 0D 0A
00 6F 70 5F 63 6F 6E 64 20 65 72 72 6F 72 0D 0A
00 49 46 20 43 6F 6E 64 0D 0A 00 47 6F 20 49 44
4C 45 0D 0A 00 25 32 78 00 0D 0A 00 30 31 32 33
34 35 36 37 38 39 41 42 43 44 45 46 2D 32 31 34
37 34 38 33 36 34 38 00 00 01 02 0C 09 0A 10 40
50 A0 D0 66 66 66 66 A6 88 88 66 66 66 66 66 66
66 66 66 09 00 00 00 00 00 00 00 33 33 33 33 33
00 00 00 50 55 55 25 22 22 22 22 22 22 22 22 22
02 00 00 40 44 44 14 11 11 11 11 11 11 11 11 11
01 00 70 00 00 00 00 00 00 00 00 00 00 00 00 00
92 AE 01 92 20 BB F5 4C 2B F3 A0 06 A2 00 B1 04
A2 00 29 F0 20 1E FA D0 03 4C 16 F3 A9 FE A2 FD
20 99 FA 4C 2B F3 A9 E6 A2 FD 20 CC FC A0 08 A2
00 B1 04 20 CC FC A0 04 20 65 FA 6C 00 92 4C 31
F3 4C 31 F3 A0 0C 20 04 FA 60 20 00 FB A9 00 20
B6 FC 20 6E F1 4C 71 F3 A0 00 A2 00 18 A9 01 71
04 91 04 A0 00 A2 00 B1 04 C9 FF 20 3D FC D0 03
4C 71 F3 A9 24 A2 FE 20 99 FA A2 00 A9 01 4C 27
F4 20 2B F4 A0 01 91 04 C9 01 20 37 FC D0 C9 A9
01 20 57 FB 20 48 F4 A0 01 A2 00 B1 04 C9 01 20
37 FC D0 03 4C A5 F3 A9 1B A2 FE 20 99 FA A2 00
A9 01 4C 27 F4 A0 05 A2 00 B1 04 C9 AA 20 37 FC
D0 03 4C BC F3 A2 00 A9 01 4C 27 F4 A2 00 A9 00
A0 00 91 04 A0 00 A2 00 B1 04 C9 FF 20 3D FC D0
03 4C E2 F3 A9 0C A2 FE 20 99 FA A2 00 A9 01 4C
27 F4 20 6A F5 A0 01 91 04 A0 01 A2 00 B1 04 C9
02 20 56 FC D0 03 4C 00 F4 20 87 F5 A0 01 91 04
A0 00 A2 00 18 A9 01 71 04 91 04 A0 01 A2 00 B1
04 C9 00 20 37 FC D0 AC A9 01 20 57 FB 20 F0 F4
A2 00 A9 00 4C 27 F4 20 2D FB 60 A2 00 A9 00 20
B6 FC A2 00 86 06 86 07 A9 00 20 8A FB A2 00 A9
94 20 43 F1 4C 47 F4 60 20 CC FC A2 00 A9 FF 20
3F F2 A2 00 A9 00 20 33 F2 A2 00 A9 FF 20 3F F2
A2 00 A9 08 20 B6 FC A2 01 A9 00 85 06 A9 00 85
07 A9 AA 20 8A FB A2 00 A9 86 20 CE F0 A0 01 20
3D FB 20 25 F1 A2 00 A9 FF 20 3F F2 A2 00 A9 00
20 39 F2 A2 00 A9 FF 20 3F F2 20 15 FB 60 20 CC
FC A2 00 A9 FF 20 3F F2 A2 00 A9 00 20 33 F2 A2
00 A9 FF 20 3F F2 A2 00 A9 0D 20 B6 FC A2 00 86
06 86 07 A9 00 20 8A FB A2 00 A9 00 20 CE F0 A0
01 20 3D FB 20 FA F0 A2 00 A9 FF 20 3F F2 A2 00
A9 00 20 39 F2 A2 00 A9 FF 20 3F F2 20 15 FB 60
20 CC FC 20 D0 FA A2 00 A9 FF 20 3F F2 A2 00 A9
00 20 33 F2 A2 00 A9 FF 20 3F F2 A0 00 91 04 A0
00 A2 00 B1 04 C9 FF 20 37 FC D0 03 4C 30 F5 4C
22 F5 A2 00 A9 FF 20 3F F2 C9 FF 20 37 FC D0 F2
A2 00 A9 3A 20 B6 FC A2 00 86 06 86 07 A9 00 20
8A FB A2 00 A9 00 20 CE F0 A0 02 20 3D FB 20 25
F1 A2 00 A9 FF 20 3F F2 A2 00 A9 00 20 39 F2 A2
00 A9 FF 20 3F F2 20 23 FB 60 A2 00 A9 37 20 B6
FC A2 00 86 06 86 07 A9 00 20 8A FB A2 00 A9 00
20 43 F1 4C 86 F5 60 A2 00 A9 29 20 B6 FC A2 00
86 06 A9 40 85 07 A9 00 20 8A FB A2 00 A9 00 20
43 F1 4C A5 F5 60 20 CC FC 20 F3 FA A0 03 A2 00
B1 04 4C B5 F5 A0 0E 20 04 FA 60 20 CC FC A9 00
20 B6 FC 20 D9 FA A2 00 A9 00 A0 00 20 E4 FC A0
01 20 3D FB E0 02 20 56 FC F0 03 4C E1 F5 4C 43
F6 A9 2D A2 FE 20 CC FC A0 06 20 3D FB A0 00 20
32 FB 20 CC FC A0 07 A2 00 A9 01 20 F4 F9 A0 04
20 65 FA A0 02 A2 00 B1 04 C9 1F 20 3D FC D0 03
4C 25 F6 A9 31 A2 FE 20 99 FA A2 00 A9 00 A0 02
91 04 4C 37 F6 A2 00 A9 20 20 68 F0 A0 02 A2 00
18 A9 01 71 04 91 04 A0 00 A2 00 A9 01 20 F4 F9
4C CF F5 A9 31 A2 FE 20 99 FA 20 28 FB 60 A0 00
B1 1A E6 1A D0 02 E6 1B 60 AD 4A 92 8D 45 92 20
FA F6 A9 45 A2 92 20 CC FC 20 AD FC 4C 02 92 A5
18 38 E9 02 85 18 B0 02 C6 19 60 AD 4F 92 D0 11
20 98 F6 4C 17 FA AD 4F 92 D0 06 20 98 F6 4C 11
FA 20 98 F6 85 06 86 07 20 6F F6 A0 01 B1 18 AA
88 B1 18 60 A0 00 84 0C 84 0D B1 1A 38 E9 30 90
2C C9 0A B0 28 20 52 F6 48 A5 0C A6 0D 06 0C 26
0D 06 0C 26 0D 65 0C 85 0C 8A 65 0D 85 0D 06 0C
26 0D 68 65 0C 85 0C 90 D1 E6 0D B0 CD A5 0C A6
0D 60 AC 51 92 EE 51 92 99 52 92 60 A9 52 A2 92
18 6D 51 92 90 01 E8 4C CC FC A5 1C A6 1D 4C CC
FC 20 59 F6 EE 4B 92 D0 F8 EE 4C 92 D0 F3 60 20
FA F6 AD 66 92 AE 67 92 20 CC FC AD 68 92 AE 69
92 20 CC FC 4C 02 92 84 0C 20 8A FB 20 EC F6 A5
0C 4C BA FB 84 0C 20 8A FB 20 EC F6 A5 0C 4C FB
FB 48 A0 05 B9 18 00 99 3F 92 88 10 F7 68 85 18
86 19 20 0D FB 85 1A 86 1B 20 0D FB 85 1C 86 1D
A9 00 A8 91 1C C8 91 1C C8 B1 1C 8D 03 92 C8 B1
1C 8D 04 92 A5 1A 85 0C A5 1B 85 0D A0 00 B1 1A
F0 0B C9 25 F0 07 C8 D0 F5 E6 1B D0 F1 98 18 65
1A 85 1A 90 02 E6 1B 38 E5 0C 85 0E A5 1B E5 0D
85 0F 05 0E F0 25 20 F3 FA A0 05 A5 1D 91 04 88
A5 1C 91 04 88 A5 0D 91 04 88 A5 0C 91 04 88 A5
0F 91 04 88 A5 0E 91 04 20 02 92 20 4E F6 AA D0
0B A2 05 BD 3F 92 95 18 CA 10 F8 60 C9 25 D0 09
B1 1A C9 25 D0 09 20 52 F6 20 5C F6 4C 74 F7 A9
00 A2 0B 9D 46 92 CA 10 FA B1 1A C9 2D D0 05 8E
46 92 F0 19 C9 2B D0 05 8E 47 92 F0 10 C9 20 D0
05 8E 48 92 F0 07 C9 23 D0 09 8E 49 92 20 52 F6
4C F9 F7 A2 20 C9 30 D0 06 AA 20 52 F6 B1 1A 8E
4A 92 C9 2A D0 09 20 52 F6 20 98 F6 4C 42 F8 20
A4 F6 8D 4B 92 8E 4C 92 8C 4D 92 8C 4E 92 B1 1A
C9 2E D0 1B 20 52 F6 B1 1A C9 2A D0 09 20 52 F6
20 98 F6 4C 69 F8 20 A4 F6 8D 4D 92 8E 4E 92 B1
1A C9 7A F0 19 C9 68 F0 15 C9 74 F0 11 C9 6A F0
08 C9 4C F0 04 C9 6C D0 0B A9 FF 8D 4F 92 20 52
F6 4C 6F F8 8C 51 92 A2 52 8E 66 92 A2 92 8E 67
92 20 52 F6 C9 63 D0 0D 20 98 F6 8D 52 92 A2 00
A9 01 4C 9B F9 C9 64 F0 04 C9 69 D0 2D A2 00 AD
48 92 F0 02 A2 20 AD 47 92 F0 02 A2 2B 8E 50 92
20 86 F6 A4 07 30 0B AC 50 92 F0 06 8C 52 92 EE
51 92 A0 0A 20 27 F7 4C 92 F9 C9 6E D0 15 20 98
F6 85 0C 86 0D A0 00 B1 1C 91 0C C8 B1 1C 91 0C
4C 74 F7 C9 6F D0 27 20 86 F6 AC 49 92 F0 17 48
86 14 05 14 05 06 05 07 0D 4D 92 0D 4E 92 F0 06
A9 30 20 E2 F6 68 A0 08 20 27 F7 4C 92 F9 C9 70
D0 0D A2 00 8E 4F 92 E8 8E 49 92 A9 78 D0 27 C9
73 D0 0C 20 98 F6 8D 66 92 8E 67 92 4C 92 F9 C9
75 D0 0B 20 7B F6 A0 0A 20 34 F7 4C 92 F9 C9 78
F0 04 C9 58 D0 29 48 AD 49 92 F0 0A A9 30 20 E2
F6 A9 58 20 E2 F6 20 7B F6 A0 10 20 34 F7 68 C9
78 D0 09 AD 66 92 AE 67 92 20 24 FD 4C 92 F9 4C
74 F7 AD 66 92 AE 67 92 20 0E FD 8D 68 92 8E 69
92 AD 4D 92 0D 4E 92 F0 15 AE 4D 92 EC 68 92 AD
4E 92 A8 ED 69 92 B0 06 8E 68 92 8C 69 92 38 AD
4B 92 ED 68 92 AA AD 4C 92 ED 69 92 B0 03 A9 00
AA 49 FF 8D 4C 92 8A 49 FF 8D 4B 92 AD 46 92 D0
03 20 04 F7 20 0F F7 AD 46 92 F0 03 20 04 F7 4C
74 F7 A0 00 18 71 04 91 04 48 C8 8A 71 04 91 04
AA 68 60 C8 48 18 98 65 04 85 04 90 02 E6 05 68
60 A0 FF E0 80 B0 02 A0 00 84 06 84 07 60 E0 00
D0 06 AA D0 03 A9 01 60 A2 00 8A 60 A0 00 F0 07
A9 52 A2 F0 4C 05 92 60 A9 00 85 0C A9 F0 85 0D
A9 00 85 0E A9 92 85 0F A2 CD A9 FF 85 14 A0 00
E8 F0 0D B1 0C 91 0E C8 D0 F6 E6 0D E6 0F D0 F0
E6 14 D0 EF 60 8C 6A 92 88 88 98 18 65 04 85 0C
A6 05 90 01 E8 86 0D A0 01 B1 0C AA 88 B1 0C 20
CC FC A5 0C A6 0D 20 93 FD AC 6A 92 4C 04 FA 85
0C 86 0D 20 75 F0 4C 9D FA 85 0C 86 0D A0 00 B1
0C F0 0E C8 84 14 20 68 F0 A4 14 D0 F2 E6 0D D0
EE 60 E0 00 D0 15 4A AA BD 5A FE 90 05 4A 4A 4A
4A 18 29 0F AA BD 4F FE A2 00 60 38 A9 00 AA 60
A4 04 D0 02 C6 05 C6 04 60 A5 04 38 E9 02 85 04
90 01 60 C6 05 60 A5 04 38 E9 04 85 04 90 01 60
C6 05 60 A5 04 38 E9 06 85 04 90 01 60 C6 05 60
A5 04 38 E9 07 85 04 90 01 60 C6 05 60 A0 01 B1
04 AA 88 B1 04 E6 04 F0 05 E6 04 F0 03 60 E6 04
E6 05 60 A0 03 4C 04 FA A0 05 4C 04 FA A0 08 4C
04 FA 85 0C 86 0D A2 00 B1 0C 60 A0 01 B1 04 AA
88 B1 04 60 A0 03 B1 04 85 07 88 B1 04 85 06 88
B1 04 AA 88 B1 04 60 A2 00 18 65 04 48 8A 65 05
AA 68 60 18 49 FF 69 01 48 8A 49 FF 69 00 AA A5
06 49 FF 69 00 85 06 A5 07 49 FF 69 00 85 07 68
60 A9 00 AA A0 00 84 06 84 07 48 20 E6 FA A0 03
A5 07 91 04 88 A5 06 91 04 88 8A 91 04 68 88 91
04 60 85 14 20 0D FB 85 0E 86 0F 85 10 86 11 20
9F FC 20 0D FB 85 06 86 07 60 20 A2 FB A6 07 A4
14 C0 0A D0 39 A5 06 05 0D 05 0C D0 11 E0 80 D0
0D A0 0B B9 43 FE 91 0E 88 10 F8 4C 32 FC 8A 10
1D A9 2D A0 00 91 0E E6 0E D0 02 E6 0F A5 0C A6
0D 20 63 FB 85 0C 86 0D 4C FE FB 20 A2 FB A9 00
48 A0 20 A9 00 06 0C 26 0D 26 06 26 07 2A C5 14
90 04 E5 14 E6 0C 88 D0 EC A8 B9 33 FE 48 A5 0C
05 0D 05 06 05 07 D0 D9 A0 00 68 91 0E F0 03 C8
D0 F8 A5 10 A6 11 60 D0 06 A2 00 8A 60 D0 FA A2
00 A9 01 60 F0 F9 30 F7 A2 00 8A 60 F0 02 10 EF
A2 00 8A 60 F0 E9 90 E7 A2 00 8A 60 F0 DB A2 00
8A 2A 60 20 8C FC A6 11 F0 13 B1 0C 91 0E C8 B1
0C 91 0E C8 D0 F4 E6 0D E6 0F CA D0 ED A6 10 F0
08 B1 0C 91 0E C8 CA D0 F8 4C 0D FB 85 10 86 11
20 9F FC C8 B1 04 AA 86 0F 88 B1 04 85 0E 60 A0
01 B1 04 85 0D 88 B1 04 85 0C 4C 15 FB A9 01 4C
CA FC A0 00 B1 04 A4 04 F0 07 C6 04 A0 00 91 04
60 C6 05 C6 04 91 04 60 A9 00 A2 00 48 A5 04 38
E9 02 85 04 B0 02 C6 05 A0 01 8A 91 04 68 88 91
04 60 A0 00 91 04 C8 48 8A 91 04 68 60 85 0E 86
0F 20 9F FC B1 0C D1 0E D0 0C AA F0 10 C8 D0 F4
E6 0D E6 0F D0 EE B0 03 A2 FF 60 A2 01 60 85 0E
86 0F A2 00 A0 00 B1 0E F0 08 C8 D0 F9 E6 0F E8
D0 F4 98 60 85 0C 86 0D 85 0E 86 0F A0 00 B1 0C
F0 14 20 B6 FA 29 02 F0 06 B1 0C 69 20 91 0C C8
D0 EC E6 0D D0 E8 A5 0E A6 0F 60 20 0D FB 85 0E
86 0F E8 8E 31 92 AA E8 8E 30 92 20 9F FC 20 0D
FB 85 10 86 11 A0 00 84 14 B1 10 18 65 0E 91 10
C8 B1 10 65 0F 91 10 CE 30 92 F0 11 A4 14 B1 0C
C8 D0 02 E6 0D 84 14 20 68 F0 4C 77 FD CE 31 92
D0 EA 60 85 0C 86 0D A9 00 8D 2A 92 8D 2B 92 A0
01 B1 04 AA 88 B1 04 20 CC FC A0 02 A9 2A 91 04
C8 A9 92 91 04 A5 0C A6 0D 20 41 F7 AD 2A 92 AE
2B 92 60 A9 32 85 0C A9 92 85 0D A9 00 A8 A2 00
F0 0A 91 0C C8 D0 FB E6 0D CA D0 F6 C0 39 F0 05
91 0C C8 D0 F7 60 62 61 64 20 74 6F 6B 65 6E 3A
20 25 78 0A 00 53 75 63 63 65 73 73 0A 00 45 72
72 6F 72 0A 00 53 74 61 72 74 0A 00 6F 70 5F 63
6F 6E 64 20 65 72 72 6F 72 0A 00 49 46 20 43 6F
6E 64 0A 00 47 6F 20 49 44 4C 45 0A 00 25 32 78
00 0A 00 30 31 32 33 34 35 36 37 38 39 41 42 43
44 45 46 2D 32 31 34 37 34 38 33 36 34 38 00 00
01 02 0C 09 0A 10 40 50 A0 D0 66 66 66 66 A6 88
88 66 66 66 66 66 66 66 66 66 09 00 00 00 00 00
00 00 33 33 33 33 33 00 00 00 50 55 55 25 22 22
22 22 22 22 22 22 22 02 00 00 40 44 44 14 11 11
11 11 11 11 11 11 11 01 00 70 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

54
hw/efinix_fpga/simulation/Makefile
View File

@@ -1,20 +1,48 @@
TARGETS= timer interrupt_controller spi_controller
TB=$(patsubst %, %_tb.sv, $(TARGETS))
SRCS=$(shell find src/ -type f -name "*.*v")
SRCS+=$(shell find ../ip/ -type f -name "*.*v" -not \( -name "*tmpl*" \))
SRCS+=$(shell find ../src/ -type f -name "*.*v")
all: $(TARGETS)
INC=$(shell find include/ -type f)
timer: timer_tb.sv
iverilog -g2005-sv -s sim -o $@ $@_tb.sv ../$@.sv
TEST_PROGRAM_NAME?=loop_test
TEST_FOLDER?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)
TEST_PROGRAM?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).hex
spi_controller: spi_controller_tb.sv ../spi_controller.sv
iverilog -g2005-sv -s sim -o $@ $@_tb.sv ../$@.sv
SD_IMAGE_PATH?=$(REPO_TOP)/sw/script/fs.fat.hex
interrupt_controller: interrupt_controller_tb.sv
iverilog -g2005-sv -s sim -o $@ $@_tb.sv ../$@.sv
#TODO implement something like sources.list
TOP_MODULE=sim_top
TARGET=sim_top
INIT_MEM=init_hex.mem
SD_IMAGE=sd_image.mem
FLAGS=-DSIM -DRTL_SIM
all: sim
.PHONY: sim
sim: $(TARGET)
vvp $(TARGET) -fst
.PHONY: full_sim
full_sim: $(TARGET) $(SD_IMAGE)
vvp $(TARGET) -fst
$(TARGET): $(INIT_MEM) $(SRCS)
iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
$(INIT_MEM):
$(MAKE) -C $(TEST_FOLDER)
cp $(TEST_PROGRAM) ./init_hex.mem
# The script that makes this file uses relative paths
$(SD_IMAGE):
sh $(REPO_TOP)/sw/script/create_verilog_image.sh
cp $(SD_IMAGE_PATH) $(SD_IMAGE)
.PHONY: clean
clean:
rm -f $(TARGETS)
rm -f *.vcd
rm -f *.vvp
rm -rf $(TARGET)
rm -rf $(INIT_MEM)
rm -rf $(SD_IMAGE)

80
hw/efinix_fpga/simulation/include/super6502_sdram_controller_define.vh Normal file
View File

@@ -0,0 +1,80 @@
// =============================================================================
// Generated by efx_ipmgr
// Version: 2023.1.150
// IP Version: 5.0
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam fSYS_MHz = 100;
localparam fCK_MHz = 200;
localparam tIORT_u = 2;
localparam CL = 3;
localparam BL = 1;
localparam DDIO_TYPE = "SOFT";
localparam DQ_WIDTH = 8;
localparam DQ_GROUP = 2;
localparam BA_WIDTH = 2;
localparam ROW_WIDTH = 13;
localparam COL_WIDTH = 9;
localparam tPWRUP = 200000;
localparam tRAS = 44;
localparam tRAS_MAX = 120000;
localparam tRC = 66;
localparam tRCD = 20;
localparam tREF = 64000000;
localparam tRFC = 66;
localparam tRP = 20;
localparam tWR = 2;
localparam tMRD = 2;
localparam SDRAM_MODE = "Native";
localparam DATA_RATE = 2;
localparam AXI_AWADDR_WIDTH = 24;
localparam AXI_WDATA_WIDTH = 32;
localparam AXI_ARADDR_WIDTH = 24;
localparam AXI_RDATA_WIDTH = 32;
localparam AXI_AWID_WIDTH = 4;
localparam AXI_AWUSER_WIDTH = 2;
localparam AXI_WUSER_WIDTH = 2;
localparam AXI_BID_WIDTH = 4;
localparam AXI_BUSER_WIDTH = 2;
localparam AXI_ARID_WIDTH = 4;
localparam AXI_ARUSER_WIDTH = 3;
localparam AXI_RUSER_WIDTH = 3;

76
hw/efinix_fpga/simulation/interrupt_controller_tb.sv
View File

@@ -1,76 +0,0 @@
module sim();
timeunit 10ns;
timeprecision 1ns;
logic clk;
logic reset;
logic [2:0] addr;
logic [7:0] i_data;
logic [7:0] o_data;
logic cs;
logic rwb;
logic irqb_master;
logic irqb0, irqb1, irqb2, irqb3, irqb4, irqb5, irqb6, irqb7;
interrupt_controller dut(
.*);
always #100 clk = clk === 1'b0;
task write_reg(input logic [2:0] _addr, input logic [7:0] _data);
@(negedge clk);
cs <= '1;
addr <= _addr;
rwb <= '0;
i_data <= '1;
@(posedge clk);
i_data <= _data;
@(negedge clk);
cs <= '0;
rwb <= '1;
endtask
task read_reg(input logic [2:0] _addr, output logic [7:0] _data);
@(negedge clk);
cs <= '1;
addr <= _addr;
rwb <= '1;
i_data <= '1;
@(posedge clk);
_data <= o_data;
@(negedge clk);
cs <= '0;
rwb <= '1;
endtask
initial
begin
$dumpfile("interrupt_controller.vcd");
$dumpvars(0,sim);
end
initial begin
reset <= '1;
irqb0 <= '1;
irqb1 <= '1;
irqb2 <= '1;
irqb3 <= '1;
irqb4 <= '1;
irqb5 <= '1;
irqb6 <= '1;
irqb7 <= '1;
repeat(5) @(posedge clk);
reset <= '0;
repeat(5) @(posedge clk);
irqb0 <= '0;
repeat(5) @(posedge clk);
$finish();
end
endmodule

102
hw/efinix_fpga/simulation/spi_controller_tb.sv
View File

@@ -1,102 +0,0 @@
module sim();
timeunit 10ns;
timeprecision 1ns;
logic clk_50;
logic i_clk;
logic i_rst;
logic i_cs;
logic i_rwb;
logic [1:0] i_addr;
logic [7:0] i_data;
logic [7:0] o_data;
logic o_spi_cs;
logic o_spi_clk;
logic o_spi_mosi;
logic i_spi_miso;
spi_controller dut(.*);
always #1 clk_50 = clk_50 === 1'b0;
always #100 i_clk = i_clk === 1'b0;
task write_reg(input logic [2:0] _addr, input logic [7:0] _data);
@(negedge i_clk);
i_cs <= '1;
i_addr <= _addr;
i_rwb <= '0;
i_data <= '1;
@(posedge i_clk);
i_data <= _data;
@(negedge i_clk);
i_cs <= '0;
i_rwb <= '1;
endtask
task read_reg(input logic [2:0] _addr, output logic [7:0] _data);
@(negedge i_clk);
i_cs <= '1;
i_addr <= _addr;
i_rwb <= '1;
i_data <= '1;
@(posedge i_clk);
_data <= o_data;
@(negedge i_clk);
i_cs <= '0;
i_rwb <= '1;
endtask
initial
begin
$dumpfile("spi_controller.vcd");
$dumpvars(0,sim);
end
logic [7:0] data;
initial begin
i_rst <= '1;
repeat(5) @(posedge i_clk);
i_cs <= '0;
i_rwb <= '1;
i_addr <= '0;
i_rst <= '0;
repeat(5) @(posedge i_clk);
write_reg(3, 1);
write_reg(2, 8'hFF);
data = (1 << 7);
while(data & (1 << 7)) begin
read_reg(3, data);
end
write_reg(3, 0);
read_reg(1, data);
assert(data == 8'h55);
repeat(50) @(posedge i_clk);
$finish();
end
logic [7:0] _spi_device_data;
initial begin
_spi_device_data <= 8'h55;
end
always @(edge o_spi_clk) begin
if (o_spi_cs == '0) begin
if (o_spi_clk == '1)
i_spi_miso <= _spi_device_data[7];
if (o_spi_clk == '0)
_spi_device_data <= _spi_device_data << 1;
end
end
endmodule

1145
hw/efinix_fpga/simulation/src/generic_sdr.v Normal file
View File

File diff suppressed because it is too large Load Diff

177
hw/efinix_fpga/simulation/src/sim_top.sv Normal file
View File

@@ -0,0 +1,177 @@
`timescale 1ns/1ps
module sim_top();
`include "include/super6502_sdram_controller_define.vh"
logic r_sysclk, r_sdrclk, r_clk_50, r_clk_cpu;
// clk_100
initial begin
r_sysclk <= '1;
forever begin
#5 r_sysclk <= ~r_sysclk;
end
end
// clk_200
initial begin
r_sdrclk <= '1;
forever begin
#2.5 r_sdrclk <= ~r_sdrclk;
end
end
// clk_50
initial begin
r_clk_50 <= '1;
forever begin
#10 r_clk_50 <= ~r_clk_50;
end
end
// clk_cpu
initial begin
r_clk_cpu <= '1;
forever begin
#125 r_clk_cpu <= ~r_clk_cpu;
end
end
// initial begin
// #275000 $finish();
// end
initial begin
$dumpfile("sim_top.vcd");
$dumpvars(0,sim_top);
end
logic button_reset;
initial begin
button_reset <= '0;
repeat(10) @(r_clk_cpu);
button_reset <= '1;
repeat(1000000) @(r_clk_cpu);
$finish();
end
logic w_cpu_reset;
logic [15:0] w_cpu_addr;
logic [7:0] w_cpu_data_from_cpu, w_cpu_data_from_dut;
logic w_cpu_rdy;
logic w_cpu_we;
logic w_cpu_phi2;
//TODO: this
cpu_65c02 u_cpu(
.phi2(w_cpu_phi2),
.reset(~w_cpu_reset),
.AB(w_cpu_addr),
.RDY(w_cpu_rdy),
.IRQ('0),
.NMI('0),
.DI_s1(w_cpu_data_from_dut),
.DO(w_cpu_data_from_cpu),
.WE(w_cpu_we)
);
logic w_dut_uart_rx, w_dut_uart_tx;
sim_uart u_sim_uart(
.clk_50(r_clk_50),
.reset(~w_cpu_reset),
.rx_i(w_dut_uart_tx),
.tx_o(w_dut_uart_rx)
);
logic w_sd_cs;
logic w_spi_clk;
logic w_spi_mosi;
logic w_spi_miso;
sd_card_emu u_sd_card_emu(
.rst(~w_cpu_reset),
.clk(w_spi_clk),
.cs(w_sd_cs),
.mosi(w_spi_mosi),
.miso(w_spi_miso)
);
super6502 u_dut(
.i_sysclk(r_sysclk),
.i_sdrclk(r_sdrclk),
.i_tACclk(~r_sdrclk),
.clk_50(r_clk_50),
.clk_cpu(r_clk_cpu),
.button_reset(button_reset),
.cpu_resb(w_cpu_reset),
.cpu_addr(w_cpu_addr),
.cpu_data_out(w_cpu_data_from_dut),
.cpu_data_in(w_cpu_data_from_cpu),
.cpu_rwb(~w_cpu_we),
.cpu_rdy(w_cpu_rdy),
.cpu_phi2(w_cpu_phi2),
.uart_rx(w_dut_uart_rx),
.uart_tx(w_dut_uart_tx),
.sd_cs(w_sd_cs),
.spi_clk(w_spi_clk),
.spi_mosi(w_spi_mosi),
.spi_miso(w_spi_miso),
.o_sdr_CKE(w_sdr_CKE),
.o_sdr_n_CS(w_sdr_n_CS),
.o_sdr_n_WE(w_sdr_n_WE),
.o_sdr_n_RAS(w_sdr_n_RAS),
.o_sdr_n_CAS(w_sdr_n_CAS),
.o_sdr_BA(w_sdr_BA),
.o_sdr_ADDR(w_sdr_ADDR),
.i_sdr_DATA(w_sdr_DQ),
.o_sdr_DATA(w_sdr_DATA),
.o_sdr_DATA_oe(w_sdr_DATA_oe),
.o_sdr_DQM(w_sdr_DQM)
);
wire w_sdr_CKE;
wire w_sdr_n_CS;
wire w_sdr_n_WE;
wire w_sdr_n_RAS;
wire w_sdr_n_CAS;
wire [BA_WIDTH -1:0]w_sdr_BA;
wire [ROW_WIDTH -1:0]w_sdr_ADDR;
wire [DQ_GROUP *DQ_WIDTH -1:0]w_sdr_DATA;
wire [DQ_GROUP *DQ_WIDTH -1:0]w_sdr_DATA_oe;
wire [DQ_GROUP -1:0]w_sdr_DQM;
wire [DQ_GROUP *DQ_WIDTH -1:0]w_sdr_DQ;
genvar i, j;
generate
for (i=0; i<DQ_GROUP*DQ_WIDTH; i=i+1)
begin: DQ_map
assign w_sdr_DQ[i] = (w_sdr_DATA_oe[i])?
w_sdr_DATA[i]:1'bz;
end
for (j=0; j<DQ_GROUP; j=j+1)
begin : mem_inst
generic_sdr inst_sdr
(
.Dq(w_sdr_DQ[((j+1)*(DQ_WIDTH))-1:((j)*DQ_WIDTH)]),
.Addr(w_sdr_ADDR[ROW_WIDTH-1:0]),
.Ba(w_sdr_BA[BA_WIDTH-1:0]),
.Clk(~r_sdrclk),
.Cke(w_sdr_CKE),
.Cs_n(w_sdr_n_CS),
.Ras_n(w_sdr_n_RAS),
.Cas_n(w_sdr_n_CAS),
.We_n(w_sdr_n_WE),
.Dqm(w_sdr_DQM[j])
);
end
endgenerate
endmodule

43
hw/efinix_fpga/simulation/src/sim_uart/sim_uart.sv Normal file
View File

@@ -0,0 +1,43 @@
module sim_uart(
input clk,
input clk_50,
input reset,
input [7:0] i_data,
input rx_i,
output tx_o
);
logic tx_busy, rx_busy;
logic rx_data_valid, rx_error, rx_parity_error;
logic baud_x16_ce;
logic tx_en;
logic [7:0] tx_data, rx_data;
uart u_uart(
.tx_o ( tx_o ),
.rx_i ( rx_i ),
.tx_busy ( tx_busy ),
.rx_data ( rx_data ),
.rx_data_valid ( rx_data_valid ),
.rx_error ( rx_error ),
.rx_parity_error ( rx_parity_error ),
.rx_busy ( rx_busy ),
.baud_x16_ce ( baud_x16_ce ),
.clk ( clk_50 ),
.reset ( reset ),
.tx_data ( tx_data ),
.baud_rate ( baud_rate ),
.tx_en ( tx_en )
);
always @(posedge baud_x16_ce) begin
if (rx_data_valid)
$display("UART: %c", rx_data);
end
endmodule

1
hw/efinix_fpga/simulation/src/verilog-6502 Submodule

Submodule hw/efinix_fpga/simulation/src/verilog-6502 added at aaf4c084ef

1
hw/efinix_fpga/simulation/src/verilog-sd-emulator Submodule

Submodule hw/efinix_fpga/simulation/src/verilog-sd-emulator added at 390b7221db

75
hw/efinix_fpga/simulation/timer_tb.sv
View File

@@ -1,75 +0,0 @@
module sim();
timeunit 10ns;
timeprecision 1ns;
logic clk;
logic rwb;
logic clk_50;
logic reset;
logic [2:0] addr;
logic [7:0] i_data;
logic [7:0] o_data;
logic cs;
logic irq;
timer dut(
.*);
always #1 clk_50 = clk_50 === 1'b0;
always #100 clk = clk === 1'b0;
task write_reg(input logic [2:0] _addr, input logic [7:0] _data);
@(negedge clk);
cs <= '1;
addr <= _addr;
rwb <= '0;
i_data <= '1;
@(posedge clk);
i_data <= _data;
@(negedge clk);
cs <= '0;
rwb <= '1;
endtask
task read_reg(input logic [2:0] _addr, output logic [7:0] _data);
@(negedge clk);
cs <= '1;
addr <= _addr;
rwb <= '1;
i_data <= '1;
@(posedge clk);
_data <= o_data;
@(negedge clk);
cs <= '0;
rwb <= '1;
endtask
initial
begin
$dumpfile("timer.vcd");
$dumpvars(0,sim);
end
logic [7:0] read_data;
initial begin
reset <= '1;
repeat(5) @(posedge clk);
reset <= '0;
write_reg(5, 16);
repeat(1024) @(posedge clk);
repeat(10) begin
read_reg(0, read_data);
$display("Read: %d", read_data);
repeat(1024) @(posedge clk);
end
$finish();
end
endmodule

26
hw/efinix_fpga/src/addr_decode.sv
View File

@@ -1,26 +0,0 @@
module addr_decode
(
input [24:0] i_addr,
input config_reg_sel,
output o_rom_cs,
output o_leds_cs,
output o_timer_cs,
output o_multiplier_cs,
output o_divider_cs,
output o_uart_cs,
output o_spi_cs,
output o_sdram_cs
);
assign o_rom_cs = (i_addr >= 25'hf000 && i_addr <= 25'hffff) && ~config_reg_sel;
assign o_timer_cs = (i_addr >= 25'heff8 && i_addr <= 25'heffb) && ~config_reg_sel;
assign o_multiplier_cs = (i_addr >= 25'heff0 && i_addr <= 25'heff7) && ~config_reg_sel;
assign o_divider_cs = (i_addr >= 25'hefe8 && i_addr <= 25'hefef) && ~config_reg_sel;
assign o_uart_cs = (i_addr >= 25'hefe6 && i_addr <= 25'hefe7) && ~config_reg_sel;
assign o_spi_cs = (i_addr >= 25'hefd8 && i_addr <= 25'hefdb) && ~config_reg_sel;
assign o_leds_cs = (i_addr == 25'hefff) && ~config_reg_sel;
assign o_sdram_cs = (i_addr < 25'he000 || i_addr >= 25'h10000) && ~config_reg_sel;
endmodule

102
hw/efinix_fpga/src/sdram_adapter.sv
View File

@@ -70,10 +70,11 @@ assign o_sdr_DQM = w_sdr_DQM[0+:2];
// But basically if we are in access, and cpuclk goes low, go back to wait.
// If something actually happened, we would be in one of the read/write states.
enum bit [1:0] {ACCESS, READ_WAIT, WRITE_WAIT, WAIT} state, next_state;
enum bit [2:0] {ACCESS, PRE_READ, READ_WAIT, PRE_WRITE, WRITE_WAIT, WAIT} state, next_state;
logic w_read, w_write, w_last;
logic [23:0] w_addr, r_addr;
logic [23:0] w_read_addr, w_write_addr;
logic [23:0] r_read_addr, r_write_addr;
logic [31:0] w_data_i, w_data_o;
logic [3:0] w_dm, r_dm;
@@ -86,25 +87,15 @@ logic [31:0] r_write_data;
logic [1:0] counter, next_counter;
always @(posedge i_sysclk) begin
if (i_arst) begin
state <= WAIT;
counter <= '0;
end else begin
state <= next_state;
counter <= next_counter;
r_write_data <= w_data_i;
r_addr <= w_addr;
r_dm <= w_dm;
end
logic [7:0] o_data_next;
if (w_data_valid)
o_data <= _data;
end
logic [23:0] addr_mux_out;
logic slow_mem;
logic r_wait;
logic _r_wait;
assign o_wait = r_wait;
assign o_wait = (r_wait | slow_mem) & i_cs;
// we need to assert rdy low until a falling edge if a reset happens
@@ -126,6 +117,20 @@ always @(posedge i_sysclk or posedge i_arst) begin
end
end
end
if (i_arst) begin
state <= WAIT;
counter <= '0;
end else begin
state <= next_state;
counter <= next_counter;
r_write_data <= w_data_i;
r_read_addr <= w_read_addr;
r_write_addr <= w_write_addr;
r_dm <= w_dm;
end
o_data <= o_data_next;
end
//because of timing issues, We really need to trigger
@@ -157,10 +162,12 @@ end
always_comb begin
slow_mem = '0;
next_state = state;
next_counter = counter;
w_addr = '0;
w_read_addr = '0;
w_write_addr = '0;
w_dm = '0;
w_read = '0;
w_write = '0;
@@ -171,65 +178,81 @@ always_comb begin
unique case (state)
WAIT: begin
if (i_cs & i_cpuclk)
if (i_cs & ~i_cpuclk)
next_state = ACCESS;
end
ACCESS: begin
// only do something if selected
if (i_cs) begin
w_addr = {{i_addr[24:2]}, {1'b0}};; // divide by 2, set last bit to 0
w_read_addr = {{i_addr[24:2]}, {1'b0}}; // divide by 2, set last bit to 0
w_write_addr = {{i_addr[24:2]}, {1'b0}}; // divide by 2, set last bit to 0
addr_mux_out = w_read_addr;
if (i_rwb) begin //read
w_read = '1;
w_last = '1;
// dm is not needed for reads?
if (w_rd_ack) next_state = READ_WAIT;
next_state = PRE_READ;
end else begin //write
w_data_i = i_data << (8*i_addr[1:0]);
//w_data_i = {4{i_data}}; //does anything get through?
w_dm = ~(4'b1 << i_addr[1:0]);
next_state = PRE_WRITE;
end
end
end
PRE_WRITE: begin
w_data_i = r_write_data;
w_write_addr = r_write_addr;
addr_mux_out = w_write_addr;
w_dm = r_dm;
//w_data_i = {4{i_data}}; //does anything get through?
if (~i_cpuclk) begin
w_write = '1;
w_last = '1;
next_state = WRITE_WAIT;
end
end
end
end
WRITE_WAIT: begin
// stay in this state until write is acknowledged.
w_write_addr = r_write_addr;
addr_mux_out = w_write_addr;
w_write = '1;
w_last = '1;
w_data_i = r_write_data;
w_dm = r_dm;
w_addr = r_addr;
if (w_wr_ack) next_state = WAIT;
end
PRE_READ: begin
w_read_addr = r_read_addr;
addr_mux_out = w_read_addr;
w_read = '1;
w_last = '1;
slow_mem = '1;
// dm is not needed for reads?
if (w_rd_ack) next_state = READ_WAIT;
end
READ_WAIT: begin
w_read_addr = r_read_addr;
addr_mux_out = w_read_addr;
slow_mem = '1;
if (w_rd_valid) begin
w_data_valid = '1;
_data = w_data_o[8*i_addr[1:0]+:8];
end
// you must wait until the next cycle!
if (~i_cpuclk) begin
if (w_data_valid) begin
next_state = WAIT;
end
end
endcase
end
//this seems scuffed
logic [23:0] addr_mux_out;
always_comb begin
if (state == ACCESS) begin
addr_mux_out = w_addr;
if (w_data_valid) begin
o_data_next = _data;
end else begin
addr_mux_out = r_addr;
o_data_next = o_data;
end
end
@@ -245,10 +268,11 @@ logic [3:0] o_dbg_BA;
logic [25:0] o_dbg_ADDR;
logic [31:0] o_dbg_DATA_out;
logic [31:0] o_dbg_DATA_in;
logic o_sdr_init_done;
logic sdr_init_done;
logic [3:0] o_sdr_state;
assign o_ref_req = o_dbg_ref_req;
assign o_sdr_init_done = sdr_init_done;
sdram_controller u_sdram_controller(
@@ -265,7 +289,7 @@ sdram_controller u_sdram_controller(
.i_din(r_write_data), //Data to write to SDRAM. Twice normal width when running at half speed (hence the even addresses)
.i_dm(r_dm), //dm (r_dm)
.o_dout(w_data_o), //Data read from SDRAM, doubled as above.
.o_sdr_init_done(o_sdr_init_done), //Indicates that the SDRAM initialization is done.
.o_sdr_init_done(sdr_init_done), //Indicates that the SDRAM initialization is done.
.o_wr_ack(w_wr_ack), //Write acknowledge, handshake with we
.o_rd_ack(w_rd_ack), //Read acknowledge, handshake with re
.o_rd_valid(w_rd_valid),//Read valid. The data on o_dout is valid

1
hw/efinix_fpga/src/spi_controller.sv
View File

@@ -90,6 +90,7 @@ always_comb begin
1: o_data = r_input_data;
2:;
3: o_data = {active, r_control[6:0]};
default: o_data = 'x;
endcase
end

48
hw/efinix_fpga/src/super6502.sv
View File

@@ -15,7 +15,7 @@ module super6502
input button_reset,
input pll_cpu_locked,
input clk_50,
input clk_2,
input clk_cpu,
input logic [15:0] cpu_addr,
output logic [7:0] cpu_data_out,
output logic [7:0] cpu_data_oe,
@@ -60,11 +60,11 @@ assign cpu_nmib = '1;
logic w_wait;
assign cpu_rdy = ~w_wait;
assign cpu_phi2 = clk_2;
assign cpu_phi2 = clk_cpu;
logic w_sdr_init_done;
always @(posedge clk_2) begin
always @(posedge clk_cpu) begin
if (button_reset == '0) begin
cpu_resb <= '0;
end
@@ -94,18 +94,6 @@ logic w_uart_cs;
logic w_mapper_cs;
logic w_spi_cs;
addr_decode u_addr_decode(
.i_addr(w_sdram_addr),
.config_reg_sel(w_control_reg_cs),
.o_rom_cs(w_rom_cs),
.o_leds_cs(w_leds_cs),
.o_timer_cs(w_timer_cs),
.o_multiplier_cs(w_multiplier_cs),
.o_divider_cs(w_divider_cs),
.o_uart_cs(w_uart_cs),
.o_spi_cs(w_spi_cs),
.o_sdram_cs(w_sdram_cs)
);
logic [7:0] w_rom_data_out;
logic [7:0] w_leds_data_out;
@@ -118,6 +106,16 @@ logic [7:0] w_mapper_data_out;
logic [7:0] w_sdram_data_out;
always_comb begin
w_rom_cs = cpu_addr >= 16'hf000 && cpu_addr <= 16'hffff;
w_timer_cs = cpu_addr >= 16'heff8 && cpu_addr <= 16'heffb;
w_multiplier_cs = cpu_addr >= 16'heff0 && cpu_addr <= 16'heff7;
w_divider_cs = cpu_addr >= 16'hefe8 && cpu_addr <= 16'hefef;
w_uart_cs = cpu_addr >= 16'hefe6 && cpu_addr <= 16'hefe7;
w_spi_cs = cpu_addr >= 16'hefd8 && cpu_addr <= 16'hefdb;
w_leds_cs = cpu_addr == 16'hefff;
w_sdram_cs = cpu_addr < 16'he000;
if (w_rom_cs)
cpu_data_out = w_rom_data_out;
else if (w_leds_cs)
@@ -154,13 +152,13 @@ mapper u_mapper(
);
rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom(
.addr(w_sdram_addr[11:0]),
.clk(clk_2),
.addr(cpu_addr[11:0]),
.clk(clk_cpu),
.data(w_rom_data_out)
);
leds u_leds(
.clk(clk_2),
.clk(clk_cpu),
.i_data(cpu_data_in),
.o_data(w_leds_data_out),
.cs(w_leds_cs),
@@ -171,7 +169,7 @@ leds u_leds(
logic w_timer_irqb;
timer u_timer(
.clk(clk_2),
.clk(clk_cpu),
.reset(~cpu_resb),
.i_data(cpu_data_in),
.o_data(w_timer_data_out),
@@ -182,7 +180,7 @@ timer u_timer(
);
multiplier u_multiplier(
.clk(clk_2),
.clk(clk_cpu),
.reset(~cpu_resb),
.i_data(cpu_data_in),
.o_data(w_multiplier_data_out),
@@ -192,7 +190,7 @@ multiplier u_multiplier(
);
divider_wrapper u_divider(
.clk(clk_2),
.clk(clk_cpu),
.divclk(clk_50),
.reset(~cpu_resb),
.i_data(cpu_data_in),
@@ -205,7 +203,7 @@ divider_wrapper u_divider(
logic w_uart_irqb;
uart_wrapper u_uart(
.clk(clk_2),
.clk(clk_cpu),
.clk_50(clk_50),
.reset(~cpu_resb),
.i_data(cpu_data_in),
@@ -219,7 +217,7 @@ uart_wrapper u_uart(
);
spi_controller spi_controller(
.i_clk(clk_2),
.i_clk(clk_cpu),
.i_rst(~cpu_resb),
.i_cs(w_spi_cs),
.i_rwb(cpu_rwb),
@@ -235,7 +233,7 @@ spi_controller spi_controller(
sdram_adapter u_sdram_adapter(
.i_cpuclk(clk_2),
.i_cpuclk(clk_cpu),
.i_arst(~button_reset),
.i_sysclk(i_sysclk),
.i_sdrclk(i_sdrclk),
@@ -265,7 +263,7 @@ sdram_adapter u_sdram_adapter(
);
interrupt_controller u_interrupt_controller(
.clk(clk_2),
.clk(clk_cpu),
.reset(~cpu_resb),
.i_data(cpu_data_in),
.o_data(w_irq_data_out),

2
hw/efinix_fpga/src/timer.sv
View File

@@ -123,6 +123,8 @@ always_comb begin
o_data = status;
end
default: o_data = 'x;
endcase
end

6
hw/efinix_fpga/src/uart_wrapper.sv
View File

@@ -46,7 +46,7 @@ enum bit [1:0] {READY, WAIT, TRANSMIT} state, next_state;
always_ff @(posedge clk_50) begin
if (reset) begin
state = READY;
state <= READY;
irqb <= '1;
end else begin
state <= next_state;
@@ -54,6 +54,9 @@ always_ff @(posedge clk_50) begin
end
always_ff @(negedge clk) begin
if (reset) begin
status <= '0;
end else begin
status[1] <= tx_busy | tx_en;
status[0] <= status[0] | rx_data_valid;
@@ -72,6 +75,7 @@ always_ff @(negedge clk) begin
end
endcase
end
end
end

166
hw/efinix_fpga/super6502.xml
View File

@@ -1,106 +1,106 @@
<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502" description="" last_change_date="Mon Sep 18 2023 10:43:38 PM" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Sun October 15 2023 13:52:14" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion" />
<efx:device name="T20F256" />
<efx:timing_model name="C4" />
<efx:family name="Trion"/>
<efx:device name="T20F256"/>
<efx:timing_model name="C4"/>
</efx:device_info>
<efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008">
<efx:top_module name="super6502" />
<efx:design_file name="src/super6502.sv" version="default" library="default" />
<efx:design_file name="src/leds.sv" version="default" library="default" />
<efx:design_file name="src/addr_decode.sv" version="default" library="default" />
<efx:design_file name="src/sdram_adapter.sv" version="default" library="default" />
<efx:design_file name="src/timer.sv" version="default" library="default" />
<efx:design_file name="src/interrupt_controller.sv" version="default" library="default" />
<efx:design_file name="src/multiplier.sv" version="default" library="default" />
<efx:design_file name="src/divider_wrapper.sv" version="default" library="default" />
<efx:design_file name="src/uart_wrapper.sv" version="default" library="default" />
<efx:design_file name="src/sd_controller.sv" version="default" library="default" />
<efx:design_file name="src/crc7.sv" version="default" library="default" />
<efx:design_file name="src/rom.sv" version="default" library="default" />
<efx:design_file name="src/spi_controller.sv" version="default" library="default" />
<efx:design_file name="src/mapper.sv" version="default" library="default" />
<efx:top_vhdl_arch name="" />
<efx:top_module name="super6502"/>
<efx:design_file name="src/super6502.sv" version="default" library="default"/>
<efx:design_file name="src/leds.sv" version="default" library="default"/>
<efx:design_file name="src/addr_decode.sv" version="default" library="default"/>
<efx:design_file name="src/sdram_adapter.sv" version="default" library="default"/>
<efx:design_file name="src/timer.sv" version="default" library="default"/>
<efx:design_file name="src/interrupt_controller.sv" version="default" library="default"/>
<efx:design_file name="src/multiplier.sv" version="default" library="default"/>
<efx:design_file name="src/divider_wrapper.sv" version="default" library="default"/>
<efx:design_file name="src/uart_wrapper.sv" version="default" library="default"/>
<efx:design_file name="src/sd_controller.sv" version="default" library="default"/>
<efx:design_file name="src/crc7.sv" version="default" library="default"/>
<efx:design_file name="src/rom.sv" version="default" library="default"/>
<efx:design_file name="src/spi_controller.sv" version="default" library="default"/>
<efx:top_vhdl_arch name=""/>
</efx:design_info>
<efx:constraint_info>
<efx:sdc_file name="constraints/super6502.pt.sdc" />
<efx:inter_file name="" />
<efx:sdc_file name="constraints/super6502.pt.sdc"/>
<efx:inter_file name=""/>
</efx:constraint_info>
<efx:sim_info />
<efx:misc_info />
<efx:sim_info/>
<efx:misc_info/>
<efx:ip_info>
<efx:ip instance_name="sdram_controller" path="ip/sdram_controller/settings.json">
<efx:ip_src_file name="sdram_controller.v" />
<efx:ip_src_file name="sdram_controller.v"/>
</efx:ip>
<efx:ip instance_name="divider" path="ip/divider/settings.json">
<efx:ip_src_file name="divider.v" />
<efx:ip_src_file name="divider.v"/>
</efx:ip>
<efx:ip instance_name="uart" path="ip/uart/settings.json">
<efx:ip_src_file name="uart.v" />
<efx:ip_src_file name="uart.v"/>
</efx:ip>
</efx:ip_info>
<efx:synthesis tool_name="efx_map">
<efx:param name="work_dir" value="work_syn" value_type="e_string" />
<efx:param name="write_efx_verilog" value="on" value_type="e_bool" />
<efx:param name="mode" value="speed" value_type="e_option" />
<efx:param name="max_ram" value="-1" value_type="e_integer" />
<efx:param name="max_mult" value="-1" value_type="e_integer" />
<efx:param name="infer-clk-enable" value="3" value_type="e_option" />
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option" />
<efx:param name="fanout-limit" value="0" value_type="e_integer" />
<efx:param name="bram_output_regs_packing" value="1" value_type="e_option" />
<efx:param name="retiming" value="1" value_type="e_option" />
<efx:param name="seq_opt" value="1" value_type="e_option" />
<efx:param name="blast_const_operand_adders" value="1" value_type="e_option" />
<efx:param name="operator-sharing" value="0" value_type="e_option" />
<efx:param name="optimize-adder-tree" value="0" value_type="e_option" />
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option" />
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option" />
<efx:param name="min-sr-fanout" value="0" value_type="e_option" />
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option" />
<efx:param name="blackbox-error" value="1" value_type="e_option" />
<efx:param name="allow-const-ram-index" value="0" value_type="e_option" />
<efx:param name="hdl-compile-unit" value="1" value_type="e_option" />
<efx:param name="create-onehot-fsms" value="0" value_type="e_option" />
<efx:param name="min-ce-fanout" value="0" value_type="e_integer" />
<efx:param name="mult-decomp-retime" value="0" value_type="e_option" />
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option" />
<efx:param name="include" value="ip/sdram_controller" value_type="e_string" />
<efx:param name="include" value="ip/divider" value_type="e_string" />
<efx:param name="include" value="ip/uart" value_type="e_string" />
<efx:param name="work_dir" value="work_syn" value_type="e_string"/>
<efx:param name="write_efx_verilog" value="on" value_type="e_bool"/>
<efx:param name="mode" value="speed" value_type="e_option"/>
<efx:param name="max_ram" value="-1" value_type="e_integer"/>
<efx:param name="max_mult" value="-1" value_type="e_integer"/>
<efx:param name="infer-clk-enable" value="3" value_type="e_option"/>
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option"/>
<efx:param name="fanout-limit" value="0" value_type="e_integer"/>
<efx:param name="bram_output_regs_packing" value="1" value_type="e_option"/>
<efx:param name="retiming" value="1" value_type="e_option"/>
<efx:param name="seq_opt" value="1" value_type="e_option"/>
<efx:param name="blast_const_operand_adders" value="1" value_type="e_option"/>
<efx:param name="operator-sharing" value="0" value_type="e_option"/>
<efx:param name="optimize-adder-tree" value="0" value_type="e_option"/>
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option"/>
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option"/>
<efx:param name="min-sr-fanout" value="0" value_type="e_option"/>
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option"/>
<efx:param name="blackbox-error" value="1" value_type="e_option"/>
<efx:param name="allow-const-ram-index" value="0" value_type="e_option"/>
<efx:param name="hdl-compile-unit" value="1" value_type="e_option"/>
<efx:param name="create-onehot-fsms" value="0" value_type="e_option"/>
<efx:param name="min-ce-fanout" value="0" value_type="e_integer"/>
<efx:param name="mult-decomp-retime" value="0" value_type="e_option"/>
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option"/>
<efx:param name="include" value="ip/sdram_controller" value_type="e_string"/>
<efx:param name="include" value="ip/divider" value_type="e_string"/>
<efx:param name="include" value="ip/uart" value_type="e_string"/>
</efx:synthesis>
<efx:place_and_route tool_name="efx_pnr">
<efx:param name="work_dir" value="work_pnr" value_type="e_string" />
<efx:param name="verbose" value="off" value_type="e_bool" />
<efx:param name="load_delaym" value="on" value_type="e_bool" />
<efx:param name="optimization_level" value="NULL" value_type="e_option" />
<efx:param name="seed" value="1" value_type="e_integer" />
<efx:param name="placer_effort_level" value="2" value_type="e_option" />
<efx:param name="max_threads" value="-1" value_type="e_integer" />
<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
<efx:param name="verbose" value="off" value_type="e_bool"/>
<efx:param name="load_delaym" value="on" value_type="e_bool"/>
<efx:param name="optimization_level" value="NULL" value_type="e_option"/>
<efx:param name="seed" value="1" value_type="e_integer"/>
<efx:param name="placer_effort_level" value="2" value_type="e_option"/>
<efx:param name="max_threads" value="-1" value_type="e_integer"/>
</efx:place_and_route>
<efx:bitstream_generation tool_name="efx_pgm">
<efx:param name="mode" value="active" value_type="e_option" />
<efx:param name="width" value="1" value_type="e_option" />
<efx:param name="enable_roms" value="smart" value_type="e_option" />
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool" />
<efx:param name="io_weak_pullup" value="on" value_type="e_bool" />
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option" />
<efx:param name="bitstream_compression" value="off" value_type="e_bool" />
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool" />
<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option" />
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string" />
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool" />
<efx:param name="cold_boot" value="off" value_type="e_bool" />
<efx:param name="cascade" value="off" value_type="e_option" />
<efx:param name="generate_bit" value="on" value_type="e_bool" />
<efx:param name="generate_bitbin" value="off" value_type="e_bool" />
<efx:param name="generate_hex" value="on" value_type="e_bool" />
<efx:param name="generate_hexbin" value="off" value_type="e_bool" />
<efx:param name="four_byte_addressing" value="off" value_type="e_bool" />
<efx:param name="mode" value="active" value_type="e_option"/>
<efx:param name="width" value="1" value_type="e_option"/>
<efx:param name="enable_roms" value="smart" value_type="e_option"/>
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool"/>
<efx:param name="io_weak_pullup" value="on" value_type="e_bool"/>
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option"/>
<efx:param name="bitstream_compression" value="off" value_type="e_bool"/>
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool"/>
<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option"/>
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string"/>
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool"/>
<efx:param name="cold_boot" value="off" value_type="e_bool"/>
<efx:param name="cascade" value="off" value_type="e_option"/>
<efx:param name="generate_bit" value="on" value_type="e_bool"/>
<efx:param name="generate_bitbin" value="off" value_type="e_bool"/>
<efx:param name="generate_hex" value="on" value_type="e_bool"/>
<efx:param name="generate_hexbin" value="off" value_type="e_bool"/>
<efx:param name="four_byte_addressing" value="off" value_type="e_bool"/>
</efx:bitstream_generation>
<efx:debugger>
<efx:param name="work_dir" value="work_dbg" value_type="e_string" />
<efx:param name="auto_instantiation" value="off" value_type="e_bool" />
<efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string" />
<efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
<efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
<efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string"/>
</efx:debugger>
</efx:project>

9
hw/efinix_fpga/init_env.sh → init_env.sh
View File

@@ -3,6 +3,8 @@
# ENV=".env/$HOSTNAME"
export REPO_TOP=$(git rev-parse --show-toplevel)
# if [ ! -d "$ENV" ]; then
# mkdir -p "$ENV"
# fi
@@ -19,7 +21,12 @@
# source "$ENV/efinity/2023.1/bin/setup.sh"
# export PATH=$PATH:"$EFXPT_HOME/bin"
source $EFX_SETUP
if [ -n "$EFX_SETUP" ]; then
source $EFX_SETUP
else
echo "EFX_SETUP not defined!"
fi
# python -m venv .user_venv --system-site-packages
# . .user_venv/bin/activate

3
sw/.gitignore vendored
View File

@@ -53,3 +53,6 @@ modules.order
Module.symvers
Mkfile.old
dkms.conf
# Filesystem Images
*.fat

10
sw/Makefile
View File

@@ -1,6 +1,6 @@
.PHONY: all install bootloader kernel clean
.PHONY: all install bios kernel clean
all: toolchain bootloader kernel
all: toolchain bios kernel
install: all
sh script/format_disk.sh
@@ -9,14 +9,14 @@ install: all
toolchain:
@$(MAKE) -j4 -C cc65
bootloader:
@$(MAKE) -C bootloader
bios:
@$(MAKE) -C bios
kernel:
@$(MAKE) -C kernel
clean:
@$(MAKE) -C bootloader --no-print-directory $@
@$(MAKE) -C bios --no-print-directory $@
@$(MAKE) -C kernel --no-print-directory $@
@$(MAKE) -C cc65 --no-print-directory $@

4
sw/bios/Makefile
View File

@@ -1,5 +1,5 @@
CC=../cc65/bin/cl65
CFLAGS=-T -t none -I. --cpu "65C02"
CFLAGS=-T -t none -I. --cpu "65C02" -DRTL_SIM
LDFLAGS=-C link.ld -m $(NAME).map
NAME=bios
@@ -7,7 +7,7 @@ NAME=bios
BIN=$(NAME).bin
HEX=$(NAME).hex
FPGA_IMG=../../hw/efinix_fpga/init_hex.mem
FPGA_IMG=$(REPO_TOP)/hw/efinix_fpga/init_hex.mem
EFX_RUN=/home/byron/Software/efinity/2023.1/scripts/efx_run.py
EFX_PRJ=/home/byron/Projects/super6502/hw/efinix_fpga/super6502.xml

10
sw/bios/boot2.s
View File

@@ -335,10 +335,10 @@ _start:
@end: bra @end
str: .asciiz "boot2\r\n"
str: .asciiz "boot2\n"
kernel_str: .asciiz "KERNEL O65"
_good: .asciiz "Found KERNEL\r\n"
word_str: .asciiz "Word Value: %x\r\n"
_good: .asciiz "Found KERNEL\n"
word_str: .asciiz "Word Value: %x\n"
opt_str: .asciiz "Opt Len: %x, Opt Type: %x\r\n"
opt_done: .asciiz "Options done. total option length: %x\r\n"
opt_str: .asciiz "Opt Len: %x, Opt Type: %x\n"
opt_done: .asciiz "Options done. total option length: %x\n"

10
sw/bios/bootloader.s
View File

@@ -173,12 +173,12 @@ _main:
@end: bra @end
str: .asciiz "boot\r\n"
str: .asciiz "boot\n"
_boot2_str: .asciiz "BOOT2 BIN"
_fail: .asciiz "not bootloader\r\n"
_good: .asciiz "found bootloader!\r\n"
_cluster: .asciiz "cluster: %lx\r\n"
_addr: .asciiz "addr: %x\r\n"
_fail: .asciiz "not bootloader\n"
_good: .asciiz "found bootloader!\n"
_cluster: .asciiz "cluster: %lx\n"
_addr: .asciiz "addr: %x\n"
_end:
.res (440+_start-_end)

14
sw/bios/devices/sd_card.c
View File

@@ -20,17 +20,19 @@ uint8_t SD_init()
cmdAttempts++;
if(cmdAttempts == CMD0_MAX_ATTEMPTS)
{
cputs("Go IDLE\r\n");
cputs("Go IDLE\n");
return SD_ERROR;
}
}
#ifndef RTL_SIM
for (i = 0; i < 1000; i++);
#endif
SD_sendIfCond(res);
if(res[0] != SD_IN_IDLE_STATE)
{
cputs("IF Cond\r\n");
cputs("IF Cond\n");
return SD_ERROR;
}
@@ -44,7 +46,7 @@ uint8_t SD_init()
{
if(cmdAttempts == CMD55_MAX_ATTEMPTS)
{
cputs("op_cond error\r\n");
cputs("op_cond error\n");
return SD_ERROR;
}
@@ -54,13 +56,17 @@ uint8_t SD_init()
res[0] = SD_sendOpCond();
}
#ifndef RTL_SIM
for (i = 0; i < 1000; i++);
#endif
cmdAttempts++;
}
while(res[0] != SD_READY);
#ifndef RTL_SIM
for (i = 0; i < 1000; i++);
#endif
SD_readOCR(res);
@@ -304,7 +310,7 @@ void SD_sendStatus(uint8_t *res)
// while(++readAttempts != SD_MAX_READ_ATTEMPTS)
// if((read = spi_exchange(0xFF)) != 0xFF) break;
// cprintf("read attempts: %d\r\n", readAttempts);
// cprintf("read attempts: %d\n", readAttempts);
// // if response token is 0xFE
// if(read == SD_START_TOKEN)

4
sw/bios/devices/sd_print.c
View File

@@ -13,7 +13,7 @@ void SD_printBuf(uint8_t *buf)
cprintf("%2x", *buf++);
if(colCount == 31)
{
cputs("\r\n");
cputs("\n");
colCount = 0;
}
else
@@ -22,5 +22,5 @@ void SD_printBuf(uint8_t *buf)
colCount++;
}
}
cputs("\r\n");
cputs("\n");
}

10
sw/bios/main.c
View File

@@ -19,16 +19,16 @@ int main() {
uint32_t addr = 0x00000000;
uint16_t i;
cputs("Start\r\n");
cputs("Start\n");
// initialize sd card
if(SD_init() != SD_SUCCESS)
{
cputs("Error\r\n");
cputs("Error\n");
}
else
{
cputs("Success\r\n");
cputs("Success\n");
res[0] = SD_readSingleBlock(addr, buf, &token);
@@ -38,9 +38,9 @@ int main() {
//else if error token received, print
else if(!(token & 0xF0))
{
cputs("Error\r\n");
cputs("Error\n");
} else {
cprintf("bad token: %x\r\n", token);
cprintf("bad token: %x\n", token);
}
__asm__ ("jmp (%v)", buf);

2
sw/kernel/kernel.c
View File

@@ -16,7 +16,7 @@ int main() {
cprintf("%s", string);
cprintf("Here is a long string: %s\r\n", longstring);
cprintf("Here is a long string: %s\n", longstring);
while(1);

40
sw/script/create_verilog_image.sh Normal file
View File

@@ -0,0 +1,40 @@
#!/bin/bash
BOOTLOADER=$REPO_TOP/sw/bios/bootloader.bin
FILE=$REPO_TOP/sw/script/fs.fat
TMPMOUNT=/tmp/lo
FSDIR=$REPO_TOP/sw/fsdir
MNT=/run/media/$USER/SUPER6502
V=-v
# Smallest number of blocks where mkfs doesn't complain
BLOCKS=33296
rm $FILE
echo "$(tput bold setaf 11)Creating Filesystem$(tput sgr 0)"
mkfs.vfat $V -I -F32 -C $FILE -n SUPER6502 $BLOCKS
echo
echo "$(tput bold setaf 11)Modifying Boot Sector$(tput sgr 0)"
dd if=$BOOTLOADER of=$FILE bs=1 conv=notrunc count=11 $STATUS
dd if=$BOOTLOADER of=$FILE bs=1 conv=notrunc count=380 seek=71 skip=71 $STATUS
LOOP=$(udisksctl loop-setup -f $FILE | grep -o "/dev/loop\([0-9]\)\+")
MNT=$(udisksctl mount -b $LOOP $TMPMOUNT | grep -o "\([A-Za-z/-]*/\)SUPER6502")
echo "$(tput bold setaf 11)Copying Files$(tput sgr 0)"
cp $V -r $FSDIR/* $MNT
echo
udisksctl unmount -b $LOOP
udisksctl loop-delete -b $LOOP
echo "$(tput bold setaf 11)Converting Image to Verilog$(tput sgr 0)"
objcopy --input-target=binary --output-target=verilog --verilog-data-width=1 $FILE $FILE.hex
echo "$(tput bold setaf 10)Done!$(tput sgr 0)"

2
sw/script/format_disk.sh
View File

@@ -1,6 +1,6 @@
#!/bin/bash
BOOTLOADER=../bios/bootloader.bin
BOOTLOADER=$REPO_TOP/sw/bios/bootloader.bin
DEVICE=/dev/mmcblk0
TMPBOOTSECT=/tmp/bootsect
TMPMOUNT=/tmp/sd

39
sw/test_code/indirect_test/Makefile Normal file
View File

@@ -0,0 +1,39 @@
CC=../../cc65/bin/cl65
LD=../../cc65/bin/cl65
CFLAGS=-T -t none -I. --cpu "65C02"
LDFLAGS=-C link.ld -m $(NAME).map
NAME=indirect_test
BIN=$(NAME).bin
HEX=$(NAME).hex
LISTS=lists
SRCS=$(wildcard *.s) $(wildcard *.c)
SRCS+=$(wildcard **/*.s) $(wildcard **/*.c)
OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS)))
OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
# Make sure the kernel linked to correct address, no relocation!
all: $(HEX)
$(HEX): $(BIN)
objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX)
$(BIN): $(OBJS)
$(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@
%.o: %.c $(LISTS)
$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
%.o: %.s $(LISTS)
$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
$(LISTS):
mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS))))
.PHONY: clean
clean:
rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map

35
sw/test_code/indirect_test/link.ld Normal file
View File

@@ -0,0 +1,35 @@
MEMORY
{
ZP: start = $0, size = $100, type = rw, define = yes;
SDRAM: start = $9200, size = $4d00, type = rw, define = yes;
ROM: start = $F000, size = $1000, file = %O;
}
SEGMENTS {
ZEROPAGE: load = ZP, type = zp, define = yes;
DATA: load = ROM, type = rw, define = yes, run = SDRAM;
BSS: load = SDRAM, type = bss, define = yes;
HEAP: load = SDRAM, type = bss, optional = yes;
STARTUP: load = ROM, type = ro;
ONCE: load = ROM, type = ro, optional = yes;
CODE: load = ROM, type = ro;
RODATA: load = ROM, type = ro;
VECTORS: load = ROM, type = ro, start = $FFFA;
}
FEATURES {
CONDES: segment = STARTUP,
type = constructor,
label = __CONSTRUCTOR_TABLE__,
count = __CONSTRUCTOR_COUNT__;
CONDES: segment = STARTUP,
type = destructor,
label = __DESTRUCTOR_TABLE__,
count = __DESTRUCTOR_COUNT__;
}
SYMBOLS {
# Define the stack size for the application
__STACKSIZE__: value = $0200, type = weak;
__STACKSTART__: type = weak, value = $0800; # 2k stack
}

20
sw/test_code/indirect_test/main.s Normal file
View File

@@ -0,0 +1,20 @@
.export _init, _nmi_int, _irq_int
.code
_nmi_int:
_irq_int:
_init:
ldx #$ff
txs
lda #$aa
sta $01
lda #$bb
sta $00
ldy #$1
lda #$cc
sta ($00),y
@end: bra @end

14
sw/test_code/indirect_test/vectors.s Normal file
View File

@@ -0,0 +1,14 @@
; ---------------------------------------------------------------------------
; vectors.s
; ---------------------------------------------------------------------------
;
; Defines the interrupt vector table.
.import _init
.import _nmi_int, _irq_int
.segment "VECTORS"
.addr _nmi_int ; NMI vector
.addr _init ; Reset vector
.addr _irq_int ; IRQ/BRK vector

39
sw/test_code/jsr_test/Makefile Normal file
View File

@@ -0,0 +1,39 @@
CC=../../cc65/bin/cl65
LD=../../cc65/bin/cl65
CFLAGS=-T -t none -I. --cpu "65C02"
LDFLAGS=-C link.ld -m $(NAME).map
NAME=jsr_test
BIN=$(NAME).bin
HEX=$(NAME).hex
LISTS=lists
SRCS=$(wildcard *.s) $(wildcard *.c)
SRCS+=$(wildcard **/*.s) $(wildcard **/*.c)
OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS)))
OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
# Make sure the kernel linked to correct address, no relocation!
all: $(HEX)
$(HEX): $(BIN)
objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX)
$(BIN): $(OBJS)
$(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@
%.o: %.c $(LISTS)
$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
%.o: %.s $(LISTS)
$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
$(LISTS):
mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS))))
.PHONY: clean
clean:
rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map

35
sw/test_code/jsr_test/link.ld Normal file
View File

@@ -0,0 +1,35 @@
MEMORY
{
ZP: start = $0, size = $100, type = rw, define = yes;
SDRAM: start = $9200, size = $4d00, type = rw, define = yes;
ROM: start = $F000, size = $1000, file = %O;
}
SEGMENTS {
ZEROPAGE: load = ZP, type = zp, define = yes;
DATA: load = ROM, type = rw, define = yes, run = SDRAM;
BSS: load = SDRAM, type = bss, define = yes;
HEAP: load = SDRAM, type = bss, optional = yes;
STARTUP: load = ROM, type = ro;
ONCE: load = ROM, type = ro, optional = yes;
CODE: load = ROM, type = ro;
RODATA: load = ROM, type = ro;
VECTORS: load = ROM, type = ro, start = $FFFA;
}
FEATURES {
CONDES: segment = STARTUP,
type = constructor,
label = __CONSTRUCTOR_TABLE__,
count = __CONSTRUCTOR_COUNT__;
CONDES: segment = STARTUP,
type = destructor,
label = __DESTRUCTOR_TABLE__,
count = __DESTRUCTOR_COUNT__;
}
SYMBOLS {
# Define the stack size for the application
__STACKSIZE__: value = $0200, type = weak;
__STACKSTART__: type = weak, value = $0800; # 2k stack
}

23
sw/test_code/jsr_test/main.s Normal file
View File

@@ -0,0 +1,23 @@
.export _init, _nmi_int, _irq_int
.code
_nmi_int:
_irq_int:
_init:
ldx #$ff
txs
lda #$00
jsr subroutine
sta $00
@1: bra @1
subroutine:
inc
jsr suborutine2
rts
suborutine2:
inc
rts

14
sw/test_code/jsr_test/vectors.s Normal file
View File

@@ -0,0 +1,14 @@
; ---------------------------------------------------------------------------
; vectors.s
; ---------------------------------------------------------------------------
;
; Defines the interrupt vector table.
.import _init
.import _nmi_int, _irq_int
.segment "VECTORS"
.addr _nmi_int ; NMI vector
.addr _init ; Reset vector
.addr _irq_int ; IRQ/BRK vector

39
sw/test_code/loop_test/Makefile Normal file
View File

@@ -0,0 +1,39 @@
CC=../../cc65/bin/cl65
LD=../../cc65/bin/cl65
CFLAGS=-T -t none -I. --cpu "65C02"
LDFLAGS=-C link.ld -m $(NAME).map
NAME=loop_test
BIN=$(NAME).bin
HEX=$(NAME).hex
LISTS=lists
SRCS=$(wildcard *.s) $(wildcard *.c)
SRCS+=$(wildcard **/*.s) $(wildcard **/*.c)
OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS)))
OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
# Make sure the kernel linked to correct address, no relocation!
all: $(HEX)
$(HEX): $(BIN)
objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX)
$(BIN): $(OBJS)
$(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@
%.o: %.c $(LISTS)
$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
%.o: %.s $(LISTS)
$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
$(LISTS):
mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS))))
.PHONY: clean
clean:
rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map

35
sw/test_code/loop_test/link.ld Normal file
View File

@@ -0,0 +1,35 @@
MEMORY
{
ZP: start = $0, size = $100, type = rw, define = yes;
SDRAM: start = $9200, size = $4d00, type = rw, define = yes;
ROM: start = $F000, size = $1000, file = %O;
}
SEGMENTS {
ZEROPAGE: load = ZP, type = zp, define = yes;
DATA: load = ROM, type = rw, define = yes, run = SDRAM;
BSS: load = SDRAM, type = bss, define = yes;
HEAP: load = SDRAM, type = bss, optional = yes;
STARTUP: load = ROM, type = ro;
ONCE: load = ROM, type = ro, optional = yes;
CODE: load = ROM, type = ro;
RODATA: load = ROM, type = ro;
VECTORS: load = ROM, type = ro, start = $FFFA;
}
FEATURES {
CONDES: segment = STARTUP,
type = constructor,
label = __CONSTRUCTOR_TABLE__,
count = __CONSTRUCTOR_COUNT__;
CONDES: segment = STARTUP,
type = destructor,
label = __DESTRUCTOR_TABLE__,
count = __DESTRUCTOR_COUNT__;
}
SYMBOLS {
# Define the stack size for the application
__STACKSIZE__: value = $0200, type = weak;
__STACKSTART__: type = weak, value = $0800; # 2k stack
}

16
sw/test_code/loop_test/main.s Normal file
View File

@@ -0,0 +1,16 @@
.export _init, _nmi_int, _irq_int
.code
_nmi_int:
_irq_int:
_init:
lda #$00
@1: inc
sta $01
lda $01
cmp $01
beq @1
@end: bra @end

14
sw/test_code/loop_test/vectors.s Normal file
View File

@@ -0,0 +1,14 @@
; ---------------------------------------------------------------------------
; vectors.s
; ---------------------------------------------------------------------------
;
; Defines the interrupt vector table.
.import _init
.import _nmi_int, _irq_int
.segment "VECTORS"
.addr _nmi_int ; NMI vector
.addr _init ; Reset vector
.addr _irq_int ; IRQ/BRK vector

39
sw/test_code/simple_mem_test/Makefile Normal file
View File

@@ -0,0 +1,39 @@
CC=../../cc65/bin/cl65
LD=../../cc65/bin/cl65
CFLAGS=-T -t none -I. --cpu "65C02"
LDFLAGS=-C link.ld -m $(NAME).map
NAME=simple_mem_test
BIN=$(NAME).bin
HEX=$(NAME).hex
LISTS=lists
SRCS=$(wildcard *.s) $(wildcard *.c)
SRCS+=$(wildcard **/*.s) $(wildcard **/*.c)
OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS)))
OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
# Make sure the kernel linked to correct address, no relocation!
all: $(HEX)
$(HEX): $(BIN)
objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX)
$(BIN): $(OBJS)
$(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@
%.o: %.c $(LISTS)
$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
%.o: %.s $(LISTS)
$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
$(LISTS):
mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS))))
.PHONY: clean
clean:
rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map

35
sw/test_code/simple_mem_test/link.ld Normal file
View File

@@ -0,0 +1,35 @@
MEMORY
{
ZP: start = $0, size = $100, type = rw, define = yes;
SDRAM: start = $9200, size = $4d00, type = rw, define = yes;
ROM: start = $F000, size = $1000, file = %O;
}
SEGMENTS {
ZEROPAGE: load = ZP, type = zp, define = yes;
DATA: load = ROM, type = rw, define = yes, run = SDRAM;
BSS: load = SDRAM, type = bss, define = yes;
HEAP: load = SDRAM, type = bss, optional = yes;
STARTUP: load = ROM, type = ro;
ONCE: load = ROM, type = ro, optional = yes;
CODE: load = ROM, type = ro;
RODATA: load = ROM, type = ro;
VECTORS: load = ROM, type = ro, start = $FFFA;
}
FEATURES {
CONDES: segment = STARTUP,
type = constructor,
label = __CONSTRUCTOR_TABLE__,
count = __CONSTRUCTOR_COUNT__;
CONDES: segment = STARTUP,
type = destructor,
label = __DESTRUCTOR_TABLE__,
count = __DESTRUCTOR_COUNT__;
}
SYMBOLS {
# Define the stack size for the application
__STACKSIZE__: value = $0200, type = weak;
__STACKSTART__: type = weak, value = $0800; # 2k stack
}

24
sw/test_code/simple_mem_test/main.s Normal file
View File

@@ -0,0 +1,24 @@
.export _init, _nmi_int, _irq_int
.code
_nmi_int:
_irq_int:
_init:
lda #$aa
sta $10
lda #$55
sta $11
lda #$ff
sta $12
lda #$00
sta $13
lda $10
lda $11
lda $12
lda $13
@1: bra @1

14
sw/test_code/simple_mem_test/vectors.s Normal file
View File

@@ -0,0 +1,14 @@
; ---------------------------------------------------------------------------
; vectors.s
; ---------------------------------------------------------------------------
;
; Defines the interrupt vector table.
.import _init
.import _nmi_int, _irq_int
.segment "VECTORS"
.addr _nmi_int ; NMI vector
.addr _init ; Reset vector
.addr _irq_int ; IRQ/BRK vector