Add io chip select

2022-03-05 23:15:50 -06:00
parent 0ad18720bb
commit 16b50dcca7
2 changed files with 11 additions and 4 deletions
--- a/hw/fpga/addr_decode.sv
+++ b/hw/fpga/addr_decode.sv
@@ -1,10 +1,12 @@
 module addr_decode(
    input logic [15:0] addr,
    output logic ram_cs,
-    output logic rom_cs
+    output logic rom_cs,
+    output logic io_cs
 );

 assign rom_cs = addr[15];
-assign ram_cs = ~addr[15];
+assign ram_cs = ~addr[15] && addr < 16'h7ff0;
+assign io_cs = addr >= 16'h7ff0 && addr < 16'h8000;

 endmodule