Merge branch '9-initialize-the-devices' into 'master'
Resolve "Initialize the devices" Closes #9 See merge request bslathi19/super6502!46
This commit is contained in:
Byron Lathi
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doc/pic/pic.drawio.png
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60
doc/pic/pic.md
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doc/pic/pic.md
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# PIC
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## Overview
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The PIC (Programmable Interrupt Controller) supports 256 edge or level
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triggered interrupts.
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Interrupts can only be rising edge or positive level trigger. Negative edge or
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low level trigger can be accomplished by inverting the input to this module.
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When an interrupt is triggered, it remains triggered until cleared with an
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`EOI`. Currently, only the highest priority interrupt can be cleared. This
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is bad design and will be fixed soon(tm).
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## Interface
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The PIC is controlled through two 8-bit registers, `CMD` and `DAT`.
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The upepr 3 bits of `CMD` control which register is accessed, and the lower 5
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bits control the byte select.
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`EOI` is a special case: when `CMD` is 0xFF, the highest priority interrupt is
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cleared.
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### CMD
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| [7:5] | [4:0] |
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|------------------ |------------- |
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| Register Address | Byte Select |
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### DAT
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| [7:0] |
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|----------------------- |
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| Data[8*Byte_sel +: 8] |
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## Registers
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### Register Map
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| Address | Read | Write |
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|--------- |------------ |-------- |
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| 0 | IRQ Number | ~ |
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| 1 | Enable | Enable |
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| 2 | Type | Type |
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### IRQ Number
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8 bit register outputs the highest priority interrupt currently active. When
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no interrupt is active, it will output 255.
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### Enable
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256 bit enable register. When bit _n_ is set to 1, the corresponding interrupt
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_n_.
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### Type
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256 bit type register. When bit _n_ is set to 0, the corresponding interrupt
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_n_ will be edge triggered. If the bit is set to 1, the interrupt will be level
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triggered.
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doc/rtc/rtc.drawio.png
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doc/rtc/rtc.drawio.png
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82
doc/rtc/rtc.md
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82
doc/rtc/rtc.md
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# RTC
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## Overview
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The RTC is capable of keeping track of elapsed time as well as generating
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periodic interrupts. Its input frequency is (currently) the same as the CPU
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frequency. The architecture is shown below:
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The `counter` register is a 32 bit register which increments by `increment`
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every clock tick. When this value reaches `threshold`, both `output` and
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`irq_counter` are incremented by 1. When `irq_counter` reaches `irq_threshold`,
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an interrupt is generated.
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The interrupt frequency can be calculated with the following equations:
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$$ F_{out}=\frac{F_{in}\cdot{increment}}{threshold} $$
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$$ F_{irq}=\frac{F_{out}}{irq\_threshold} $$
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Where $ F_{out} $ is the frequency at which the output changes and $ F_{irq} $
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is the frequency at which interrupts occur.
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## Interface
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The RTC is controlled through two 8-bit registers, `CMD` and `DAT`.
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The upepr 4 bits of `CMD` control which register is accessed, and the lower 4
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bits control the byte select. The RTC uses 32 bit registers, so only values of
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0-3 are supported.
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### CMD
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| [7:4] | [3:2 | [1:0] |
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|------------------ |---------- |------------- |
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| Register Address | Reserved | Byte Select |
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### DAT
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| [7:0] |
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|----------------------- |
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| Data[8*Byte_sel +: 8] |
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## Registers
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### Register Map
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| Address | Read | Write |
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|--------- |--------------- |--------------- |
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| 0 | Threshold | Threshold |
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| 1 | Increment | Increment |
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| 2 | IRQ Threshold | IRQ Threshold |
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| 3 | Output | Control |
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### Threshold
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32 bit threshold register. When `counter` reaches this value, `output` and
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`irq_counter` are incremented by 1, and `counter` is reset back to 0.
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### Increment
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32 bit increment register. Every clock cycle, `counter` is incremented by
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`increment`
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### IRQ Threshold
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32 bit IRQ threshold register. When `irq_counter` reaches this value, and IRQ
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is generated and `irq_counter` is reset back to 0.
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### Output
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32 bit output register. This value ticks up.
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### Control
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| [7:2] | [1] | [0] |
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|---------- |------------ |-------- |
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| Reserved | IRQ Enable | Enable |
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8 bit Control register. Regardless of Byte Select, any write to address 3 will
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write to this register. `IRQ Enable` controls interrupt generation. `Enable` is
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a global enable. When 0, all counter registers are set to 0.
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32
sw/kernel/devices/interrupt_controller.h
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32
sw/kernel/devices/interrupt_controller.h
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#ifndef _INTERRUPT_CONTROLLER_H
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#define _INTERRUPT_CONTROLLER_H
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#include <stdint.h>
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// These need to be copied in interrupt_controller.s
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#define IRQ_CMD_ADDR 0xeffc
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#define IRQ_DAT_ADDR 0xeffd
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#define IRQ_CMD_MASK 0xe0
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#define IRQ_REG_MASK 0x1f
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#define IRQ_CMD_READIRQ 0x00
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#define IRQ_CMD_ENABLE 0x20
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#define IRQ_CMD_TYPE 0x40
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#define IRQ_CMD_EOI 0xff
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#define IRQ_EDGE 0
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#define IRQ_LEVEL 1
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void init_interrupt_controller();
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void enable_irq(uint8_t type, uint8_t irqnum);
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void disable_irq(uint8_t irqnum);
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// This should accept irqnum later.
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void send_eoi();
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#endif
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136
sw/kernel/devices/interrupt_controller.s
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136
sw/kernel/devices/interrupt_controller.s
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.MACPACK generic
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.autoimport
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.importzp tmp1, tmp2
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.export _init_interrupt_controller
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.export _enable_irq
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.export _disable_irq
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.export _send_eoi
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IRQ_CMD_ADDR = $effc
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IRQ_DAT_ADDR = $effd
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IRQ_CMD_MASK = $e0
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IRQ_REG_MASK = $1f
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IRQ_CMD_READIRQ = $00
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IRQ_CMD_ENABLE = $20
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IRQ_CMD_TYPE = $40
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IRQ_CMD_EOI = $ff
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.code
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; void init_irq();
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; mask all IRQs, set all type to edge.
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.proc _init_interrupt_controller
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ldx #$20 ; enable
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ldy #00
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jsr cmd_all
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ldx #$40 ; edge type
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ldy #$00
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jsr cmd_all
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rts
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cmd_all: ; Send the same value to all 32 bytes
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txa
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add #$20
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sta tmp1
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loop:
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txa
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sta IRQ_CMD_ADDR
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tya
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sta IRQ_DAT_ADDR
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inx
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cpx tmp1
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blt loop
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rts
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.endproc
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; void enable_irq(uint8_t type, uint8_t irqnum);
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; in A:
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.proc _enable_irq
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; Decide which byte we need to modify by dividing by 32 (>> 5)
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pha
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lsr
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lsr
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lsr
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lsr
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lsr ; A is now bytesel
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sta tmp2 ; tmp2 is now bytesel
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add #IRQ_CMD_ENABLE
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sta IRQ_CMD_ADDR
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lda IRQ_DAT_ADDR
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sta tmp1
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pla
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and $07 ; A is now 0-7
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tax
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inx ; X is now 1-8
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lda #$01
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L1: dex
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beq L2
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asl
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bra L1
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L2: pha ; Push bit mask to stack
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ora tmp1 ; A is now 1 << (0-7) | enable
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sta IRQ_DAT_ADDR
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lda tmp2
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add #IRQ_CMD_TYPE
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sta IRQ_CMD_ADDR
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lda IRQ_DAT_ADDR
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sta tmp1
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jsr popa ; A is now type
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beq bit0
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bit1: ; set `bit` to 1
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pla
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ora tmp1
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bra L3
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bit0: ; set `bit` to 0
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pla
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eor #$ff
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and tmp1
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L3: sta IRQ_DAT_ADDR
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rts
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.endproc
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.proc _disable_irq
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; Decide which byte we need to modify by dividing by 32 (>> 5)
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pha
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lsr
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lsr
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lsr
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lsr
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lsr ; A is now bytesel
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add #IRQ_CMD_ENABLE
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sta IRQ_CMD_ADDR
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lda IRQ_DAT_ADDR
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sta tmp1
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pla
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and $07 ; A is now 0-7
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tax
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inx ; X is now 1-8
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lda #$01
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L1: dex
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beq L2
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asl
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bra L1
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L2: eor #$ff ; Invert to set enable to 0
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and tmp1 ; a is now ~(1 << (0-7)) & enable
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sta IRQ_DAT_ADDR
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rts
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.endproc
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; This should accept irqnum later.
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; void send_eoi();
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.proc _send_eoi
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lda #IRQ_CMD_EOI
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sta IRQ_CMD_ADDR
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lda #$1
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sta IRQ_DAT_ADDR
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rts
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.endproc
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16
sw/kernel/devices/rtc.h
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16
sw/kernel/devices/rtc.h
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@@ -0,0 +1,16 @@
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#ifndef _RTC_H
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#define _RTC_H
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#include <stdint.h>
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#define RTC_CMD_ADDR 0xeffe
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#define RTC_DAT_ADDR 0xefff
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/* initialize RTC with default values */
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void init_rtc(void);
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/* handle RTC interrupts */
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void handle_rtc(void);
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#endif
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78
sw/kernel/devices/rtc.s
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78
sw/kernel/devices/rtc.s
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@@ -0,0 +1,78 @@
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.MACPACK generic
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.importzp tmp1
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.export _init_rtc
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.export _handle_rtc
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RTC_CMD = $effe
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RTC_DAT = $efff
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RTC_THRESHOLD = $00
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RTC_INCREMENT = $10
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RTC_IRQ_THRESHOLD = $20
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RTC_OUTPUT = $30
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RTC_CONTROL = $30
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; void init_rtc(void);
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; Initialize rtc and generate 50ms interrupts
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.proc _init_rtc
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lda #RTC_INCREMENT+0 ; Set increment to 1
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sta RTC_CMD
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lda #$01
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sta RTC_DAT
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lda #RTC_INCREMENT+1
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sta RTC_CMD
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lda #$00
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sta RTC_DAT
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lda #RTC_INCREMENT+2
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sta RTC_CMD
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lda #$00
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sta RTC_DAT
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lda #RTC_INCREMENT+3
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sta RTC_CMD
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lda #$00
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sta RTC_DAT
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lda #RTC_THRESHOLD+0 ; Set threshold to 4000 ($fa0)
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sta RTC_CMD
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lda #$a0
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sta RTC_DAT
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lda #RTC_THRESHOLD+1
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sta RTC_CMD
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lda #$0f
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sta RTC_DAT
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lda #RTC_THRESHOLD+2
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sta RTC_CMD
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lda #$00
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sta RTC_DAT
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lda #RTC_THRESHOLD+3
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sta RTC_CMD
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lda #$00
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sta RTC_DAT
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lda #RTC_IRQ_THRESHOLD+0 ; Set irq threshold to 50 ($32)
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sta RTC_CMD
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lda #$32
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sta RTC_DAT
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lda #RTC_IRQ_THRESHOLD+1
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sta RTC_CMD
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lda #$00
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sta RTC_DAT
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lda #RTC_IRQ_THRESHOLD+2
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sta RTC_CMD
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lda #$00
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sta RTC_DAT
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lda #RTC_IRQ_THRESHOLD+3
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sta RTC_CMD
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lda #$00
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sta RTC_DAT
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rts
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.endproc
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.proc _handle_rtc
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nop
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rti
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.endproc
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@@ -1,25 +1,27 @@
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#include <conio.h>
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char* longstring = \
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"This is a very long string that is meant to test the loader.\
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We can only load one cluster so far, which means 8 sectors of\
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512bytes, or a total of 4k. If there was any more data than this,\
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then we would have to traverse the fat to find the next cluster number.\
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This may not be that difficult, but the file will need to be large\
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enough to actually stretch that far. The kernel will probably be\
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that big in the future, but for now when it doesnt really do anything\
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then it can't really be tested.";
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#include "devices/interrupt_controller.h"
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#include "devices/rtc.h"
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int main() {
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char* string = "this is a shorter string";
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int val = 42;
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cputs("Kernel\n");
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cprintf("Kernel printf\n");
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cprintf("Val: %d\n", val);
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cprintf("%s", string);
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cprintf("Here is a long string: %s\n", longstring);
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cputs("Kernel\n");
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// cputs("Init Paging\n")
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// init_paging()
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// cputs("Initialize Interrupts\n");
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// init_interrupts();
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cputs("Initialize Interrupt Controller\n");
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init_interrupt_controller();
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cputs("Initialize RTC\n");
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init_rtc();
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// cputs("Initialize Serial\n");
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// // init_serial();
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// enable_irq(2, IRQ_EDGE);
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while(1);
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|
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Block a user