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Add null mapper

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This commit is contained in:
Byron Lathi
2023-09-06 19:48:51 -07:00
parent a770d938de
commit 18140b32a0
5 changed files with 204 additions and 5 deletions
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2
hw/efinix_fpga/addr_decode.sv
View File

@@ -9,6 +9,7 @@ module addr_decode
output o_divider_cs,
output o_uart_cs,
output o_spi_cs,
output o_mapper_cs,
output o_sdram_cs
);
@@ -18,6 +19,7 @@ assign o_multiplier_cs = i_addr >= 16'heff0 && i_addr <= 16'heff7;
assign o_divider_cs = i_addr >= 16'hefe8 && i_addr <= 16'hefef;
assign o_uart_cs = i_addr >= 16'hefe6 && i_addr <= 16'hefe7;
assign o_spi_cs = i_addr >= 16'hefd8 && i_addr <= 16'hefdb;
assign o_mapper_cs = i_addr >= 16'hefb7 && i_addr <= 16'hefd7;
assign o_leds_cs = i_addr == 16'hefff;
assign o_sdram_cs = i_addr < 16'he000;

146
hw/efinix_fpga/debug_profile.wizard.json
View File

@@ -3,12 +3,12 @@
{
"name": "la0",
"type": "la",
"uuid": "d9fdd9521e234ab2a085f0e0ef437289",
"uuid": "2d64f403f73d428c8b583d71d6829ed4",
"trigin_en": false,
"trigout_en": false,
"auto_inserted": true,
"capture_control": false,
"data_depth": 16384,
"data_depth": 8192,
"input_pipeline": 1,
"probes": [
{
@@ -35,6 +35,11 @@
"name": "cpu_rdy",
"width": 1,
"probe_type": 1
},
{
"name": "w_sdram_addr",
"width": 25,
"probe_type": 1
}
]
}
@@ -299,6 +304,131 @@
"name": "la0_probe4",
"net": "cpu_rdy",
"path": []
},
{
"name": "la0_probe5[0]",
"net": "w_sdram_addr[0]",
"path": []
},
{
"name": "la0_probe5[1]",
"net": "w_sdram_addr[1]",
"path": []
},
{
"name": "la0_probe5[2]",
"net": "w_sdram_addr[2]",
"path": []
},
{
"name": "la0_probe5[3]",
"net": "w_sdram_addr[3]",
"path": []
},
{
"name": "la0_probe5[4]",
"net": "w_sdram_addr[4]",
"path": []
},
{
"name": "la0_probe5[5]",
"net": "w_sdram_addr[5]",
"path": []
},
{
"name": "la0_probe5[6]",
"net": "w_sdram_addr[6]",
"path": []
},
{
"name": "la0_probe5[7]",
"net": "w_sdram_addr[7]",
"path": []
},
{
"name": "la0_probe5[8]",
"net": "w_sdram_addr[8]",
"path": []
},
{
"name": "la0_probe5[9]",
"net": "w_sdram_addr[9]",
"path": []
},
{
"name": "la0_probe5[10]",
"net": "w_sdram_addr[10]",
"path": []
},
{
"name": "la0_probe5[11]",
"net": "w_sdram_addr[11]",
"path": []
},
{
"name": "la0_probe5[12]",
"net": "w_sdram_addr[12]",
"path": []
},
{
"name": "la0_probe5[13]",
"net": "w_sdram_addr[13]",
"path": []
},
{
"name": "la0_probe5[14]",
"net": "w_sdram_addr[14]",
"path": []
},
{
"name": "la0_probe5[15]",
"net": "w_sdram_addr[15]",
"path": []
},
{
"name": "la0_probe5[16]",
"net": "w_sdram_addr[16]",
"path": []
},
{
"name": "la0_probe5[17]",
"net": "w_sdram_addr[17]",
"path": []
},
{
"name": "la0_probe5[18]",
"net": "w_sdram_addr[18]",
"path": []
},
{
"name": "la0_probe5[19]",
"net": "w_sdram_addr[19]",
"path": []
},
{
"name": "la0_probe5[20]",
"net": "w_sdram_addr[20]",
"path": []
},
{
"name": "la0_probe5[21]",
"net": "w_sdram_addr[21]",
"path": []
},
{
"name": "la0_probe5[22]",
"net": "w_sdram_addr[22]",
"path": []
},
{
"name": "la0_probe5[23]",
"net": "w_sdram_addr[23]",
"path": []
},
{
"name": "la0_probe5[24]",
"net": "w_sdram_addr[24]",
"path": []
}
]
}
@@ -312,7 +442,7 @@
],
"session": {
"wizard": {
"data_depth": 16384,
"data_depth": 8192,
"capture_control": false,
"selected_nets": [
{
@@ -358,6 +488,16 @@
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": []
},
{
"name": "w_sdram_addr",
"width": 25,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": [],
"net_idx_left": 24,
"net_idx_right": 0
}
],
"top_module": "super6502",

38
hw/efinix_fpga/mapper.sv Normal file
View File

@@ -0,0 +1,38 @@
module mapper(
input clk,
input rst,
input [15:0] cpu_addr,
output logic [24:0] sdram_addr,
input cs,
input rw,
input [7:0] i_data,
output logic [7:0] o_data
);
logic [12:0] map [16];
logic [15:0] base_addr;
assign base_addr = cpu_addr - 16'hefb7;
logic en;
always_comb begin
if (!en) begin
sdram_addr = {9'b0, cpu_addr};
end
end
always_ff @(posedge clk) begin
if (rst) begin
en <= '0;
end
end
// each each entry is 4k and total address space is 64M,
// so we need 2^14 possible entries
endmodule

20
hw/efinix_fpga/super6502.sv
View File

@@ -79,6 +79,7 @@ logic w_timer_cs;
logic w_multiplier_cs;
logic w_divider_cs;
logic w_uart_cs;
logic w_mapper_cs;
logic w_spi_cs;
addr_decode u_addr_decode(
@@ -90,6 +91,7 @@ addr_decode u_addr_decode(
.o_divider_cs(w_divider_cs),
.o_uart_cs(w_uart_cs),
.o_spi_cs(w_spi_cs),
.o_mapper_cs(w_mapper_cs),
.o_sdram_cs(w_sdram_cs)
);
@@ -100,6 +102,7 @@ logic [7:0] w_multiplier_data_out;
logic [7:0] w_divider_data_out;
logic [7:0] w_uart_data_out;
logic [7:0] w_spi_data_out;
logic [7:0] w_mapper_data_out;
logic [7:0] w_sdram_data_out;
always_comb begin
@@ -119,6 +122,8 @@ always_comb begin
cpu_data_out = w_spi_data_out;
else if (w_sdram_cs)
cpu_data_out = w_sdram_data_out;
else if (w_mapper_cs)
cpu_data_out = w_mapper_data_out;
else
cpu_data_out = 'x;
end
@@ -203,6 +208,19 @@ spi_controller spi_controller(
.i_spi_miso(spi_miso)
);
logic [24:0] w_sdram_addr;
mapper u_mapper(
.clk(clk_2),
.rst(~cpu_resb),
.cpu_addr(cpu_addr),
.sdram_addr(w_sdram_addr),
.cs(w_mapper_cs),
.rw(cpu_rwb),
.i_data(cpu_data_in),
.o_data(w_mapper_data_out)
);
sdram_adapter u_sdram_adapter(
.i_cpuclk(clk_2),
@@ -214,7 +232,7 @@ sdram_adapter u_sdram_adapter(
.i_cs(w_sdram_cs),
.i_rwb(cpu_rwb),
.i_addr(cpu_addr),
.i_addr(w_sdram_addr),
.i_data(cpu_data_in),
.o_data(w_sdram_data_out),

3
hw/efinix_fpga/super6502.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Mon September 4 2023 13:53:28" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project name="super6502" description="" last_change_date="Wed September 6 2023 19:46:49" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>
@@ -20,6 +20,7 @@
<efx:design_file name="crc7.sv" version="default" library="default"/>
<efx:design_file name="rom.sv" version="default" library="default"/>
<efx:design_file name="spi_controller.sv" version="default" library="default"/>
<efx:design_file name="mapper.sv" version="default" library="default"/>
<efx:top_vhdl_arch name=""/>
</efx:design_info>
<efx:constraint_info>