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Merge branch 'master' into 48-reduce-sim-time-for-full-sim

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Byron Lathi
2023-11-18 17:42:59 -08:00
parent da2675a3fe d8199a6438
commit 19461536a2
9 changed files with 239 additions and 9 deletions
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11
hw/efinix_fpga/simulation/Makefile
View File

@@ -9,7 +9,8 @@ TEST_PROGRAM_NAME?=loop_test
TEST_FOLDER?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)
TEST_PROGRAM?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).hex
STANDALONE_TB= interrupt_controller_tb mapper_code_tb mapper_tb
STANDALONE_TB= interrupt_controller_tb mapper_tb rtc_tb
CODE_TB= interrupt_controller_code_tb mapper_code_tb
#TODO implement something like sources.list
@@ -32,15 +33,16 @@ full_sim: $(TARGET) $(SD_IMAGE)
vvp -i $(TARGET) -fst
$(STANDALONE_TB): $(SRCS) $(TBS)
iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) $(TBS)
iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) tbs/$@.sv
# mapper_code_tb: $(SRCS) $(TBS) $(INIT_MEM)
# iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) $(TBS)
$(CODE_TB): $(SRCS) $(TBS) $(INIT_MEM)
iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) tbs/$@.sv
$(TARGET): $(INIT_MEM) $(SRCS)
iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
.PHONY: $(INIT_MEM)
$(INIT_MEM):
# Make kernel
$(MAKE) -C $(REPO_TOP)/sw/kernel
@@ -58,4 +60,5 @@ clean:
rm -rf $(INIT_MEM)
rm -rf $(SD_IMAGE)
rm -rf $(STANDALONE_TB)
rm -rf $(CODE_TB)
rm -rf *.vcd

4
hw/efinix_fpga/simulation/src/sim_top.sv
View File

@@ -61,6 +61,7 @@ logic w_cpu_reset;
logic [15:0] w_cpu_addr;
logic [7:0] w_cpu_data_from_cpu, w_cpu_data_from_dut;
logic w_cpu_rdy;
logic w_cpu_irqb;
logic w_cpu_we;
logic w_cpu_phi2;
@@ -70,7 +71,7 @@ cpu_65c02 u_cpu(
.reset(~w_cpu_reset),
.AB(w_cpu_addr),
.RDY(w_cpu_rdy),
.IRQ('0),
.IRQ(~w_cpu_irqb),
.NMI('0),
.DI_s1(w_cpu_data_from_dut),
.DO(w_cpu_data_from_cpu),
@@ -114,6 +115,7 @@ super6502 u_dut(
.cpu_rwb(~w_cpu_we),
.cpu_rdy(w_cpu_rdy),
.cpu_phi2(w_cpu_phi2),
.cpu_irqb(w_cpu_irqb),
.uart_rx(w_dut_uart_rx),
.uart_tx(w_dut_uart_tx),

39
hw/efinix_fpga/simulation/tbs/interrupt_controller_code_tb.sv Normal file
View File

@@ -0,0 +1,39 @@
`timescale 1ns/1ps
module interrupt_controller_code_tb();
sim_top u_sim_top();
always begin
if (
u_sim_top.w_cpu_addr == 16'h0 &&
u_sim_top.w_cpu_we == '1
) begin
if (u_sim_top.w_cpu_data_from_cpu == 8'h6d) begin
$display("Good finish!");
$finish();
end else begin
$display("Bad finish!");
$finish_and_return(-1);
end
end
# 1;
end
initial begin
u_sim_top.u_dut.int_in = 0;
repeat (2400) @(posedge u_sim_top.r_clk_cpu);
for (int i = 0; i < 256; i++) begin
repeat (100) @(posedge u_sim_top.r_clk_cpu);
u_sim_top.u_dut.int_in = 1 << i;
$display("Activiating interrupt %d", i);
end
end
initial begin
repeat (40000) @(posedge u_sim_top.r_clk_cpu);
$display("Timed out");
$finish_and_return(-1);
end
endmodule