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Make synthesis optional

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Byron Lathi
2024-09-22 23:49:36 -07:00
parent 8784de6fe3
commit 19e4344374
2 changed files with 7 additions and 0 deletions
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2
.gitlab-ci.yml
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@@ -7,6 +7,7 @@ stages:
build:
stage: build
when: manual
tags:
- efinity
- linux
@@ -18,6 +19,7 @@ build:
sim:
stage: sim
needs: []
tags:
- linux
- efinity

5
hw/super6502_fpga/super6502_fpga.xml
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@@ -204,6 +204,11 @@
<efx:design_file name="src/sub/interfaces/axis_intf.sv" version="default" library="default" />
<efx:design_file name="src/sub/interfaces/ip_intf.sv" version="default" library="default" />
<efx:design_file name="src/sub/interfaces/eth_intf.sv" version="default" library="default" />
<efx:design_file name="src/sub/my-fifos/src/axis_saf.sv" version="default" library="default"/>
<efx:design_file name="src/sub/my-fifos/src/dpram.sv" version="default" library="default"/>
<efx:design_file name="src/sub/my-fifos/src/fifo_fwft.sv" version="default" library="default"/>
<efx:design_file name="src/sub/my-fifos/src/fifo.sv" version="default" library="default"/>
<efx:design_file name="src/sub/my-fifos/src/fwft_adapter.sv" version="default" library="default"/>
<efx:top_vhdl_arch name="" />
</efx:design_info>
<efx:constraint_info>