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update timer

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change how timer works, now counter and timer are not separate.
This commit is contained in:
Byron Lathi
2023-01-03 15:49:56 -05:00
parent 9a2f0a4bb4
commit 1ac3bdf614
3 changed files with 22 additions and 68 deletions
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2
hw/efinix_fpga/debug_profile.wizard.json
View File

@@ -3,7 +3,7 @@
{
"name": "la0",
"type": "la",
"uuid": "24a3c49eea4a40a18b701e64e40b6ba0",
"uuid": "eca5777d2e5a40ed85ba29fd5435f87f",
"trigin_en": false,
"trigout_en": false,
"auto_inserted": true,

3
hw/efinix_fpga/super6502.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Tue January 3 2023 14:11:06" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.1.226" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="change" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project name="super6502" description="" last_change_date="Tue January 3 2023 15:48:31" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>
@@ -55,6 +55,7 @@
<efx:param name="hdl-compile-unit" value="1" value_type="e_option"/>
<efx:param name="create-onehot-fsms" value="0" value_type="e_option"/>
<efx:param name="include" value="ip/sdram_controller" value_type="e_string"/>
<efx:param name="min-ce-fanout" value="0" value_type="e_integer"/>
</efx:synthesis>
<efx:place_and_route tool_name="efx_pnr">
<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>

85
hw/efinix_fpga/timer.sv
View File

@@ -10,85 +10,38 @@ module timer
output logic irq
);
logic [16:0] tick_counter_reg, irq_counter_reg;
//new idea for timer:
//it can either be oneshot or repeating
//it can either cause an interrupt or not.
//if you want it to do both, add another timer.
logic [15:0] timer_latch, timer_counter;
//control register
// bit 0: Enable interrupts
// bit 1: Enable 1 shot mode
//by default it just starts counting up
logic [7:0] divisor, status, control;
// --------------------------------
// | 0 | Tick Counter Low |
// --------------------------------
// | 1 | Tick Counter High |
// --------------------------------
// | 2 | IRQ Counter Low |
// --------------------------------
// | 3 | IRQ Counter High |
// --------------------------------
// | 4 | Control |
// --------------------------------
// | 5 | Divisor |
// --------------------------------
// | 6 | Status |
// --------------------------------
// | 7 | Reserved |
// --------------------------------
// Tick counter register
// The tick counter register is read only. It starts at 0 upon
// reset and increments continuously according to the divsor.
// IRQ Counter Register
// The IRQ counter register is writable, which is how you set the desired
// time to count down. Writing to the high register does nothing, while
// writing to the low register will begin the countdown. Based on the control
// register, the register will reset itself when it reaches 0 and triggers an
// interrupt. See the control register for more details.
// Divisor
// The divisor register controls how fast the timer counts up. The divisor is
// bit shifted left by 8 (multiplied by 256), and that is the number of pulses
// it takes to increment the counters.
// Status
// 6:0 Reserved
// 7: Interrupt. Set if an interrupt has occured. Write to clear.
// Control
// 0: Oneshot. Set if you only want the timer to run once.
// 7:1 Reserved
// What features do we want for the timer?
// 1. Tracking elapsed time
// 2. Trigger interrupts (repeated or elapsed)
// General Idea
// Takes in the input clock and can set a divisor
// of a power of 2. Every time that many clock pulses
// occur, it will increment the counter. The counter
// can then be read at any point.
// The interrupts will have a difference counter which
// counts down. When the counter reaches 0, it will trigger
// an interrupt and optionally reset the counter to start
// again.
logic [15:0] pulsecount;
logic [15:0] tickcount;
//I think this should be negedge so that writes go through
always @(negedge clk) begin
if (reset) begin
tickcount <= '0;
timer_counter <= '0;
pulsecount <= '0;
tick_counter_reg <= '0;
irq_counter_reg <= '0;
timer_latch <= '0;
divisor <= '0;
status <= '0;
control <= '0;
irq <= '1;
end else begin
if (pulsecount[15:8] == divisor) begin
tickcount <= tickcount + 16'b1;
timer_counter <= timer_counter + 16'b1;
pulsecount <= '0;
end else begin
pulsecount <= pulsecount + 16'b1;
@@ -110,11 +63,11 @@ always_comb begin
unique case (addr)
3'h0: begin
o_data = tickcount[7:0];
o_data = timer_counter[7:0];
end
3'h1: begin
o_data = tickcount[15:8];
o_data = timer_counter[15:8];
end
3'h2: begin