Decode physical addresses instead of virtual.

address decoding is now performed on the translated address which comes
from the memory mapper, instead of the address coming directly from the
cpu.

This means that you can access the full amount of ram at any address
that it is mapped to.

hw/fpga/addr_decode.sv

@@ -1,5 +1,5 @@
 module addr_decode(
-    input logic [15:0] addr,
+    input logic [23:0] addr,
     output logic sdram_cs,
     output logic rom_cs,
     output logic hex_cs,
@@ -10,13 +10,13 @@ module addr_decode(
 	output logic mm_cs2
 );
 
-assign rom_cs = addr >= 16'h8000;
-assign sdram_cs = addr < 16'h7fe0;
-assign mm_cs1 = addr >= 16'h7fe0 && addr < 16'h7ff0;
-assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff4;
-assign uart_cs = addr >= 16'h7ff4 && addr < 16'h7ff6;
-assign board_io_cs = addr == 16'h7ff6;
-assign mm_cs2 = addr == 16'h7ff7;
-assign irq_cs  = addr == 16'h7fff;
+assign rom_cs = addr >= 24'h008000 && addr < 24'h010000;
+assign sdram_cs = addr < 24'h007fe0 || addr >= 24'h010000;
+assign mm_cs1 = addr >= 24'h007fe0 && addr < 24'h007ff0;
+assign hex_cs = addr >= 24'h007ff0 && addr < 24'h007ff4;
+assign uart_cs = addr >= 24'h007ff4 && addr < 24'h007ff6;
+assign board_io_cs = addr == 24'h007ff6;
+assign mm_cs2 = addr == 24'h007ff7;
+assign irq_cs  = addr == 24'h007fff;
 
 endmodule