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Decode physical addresses instead of virtual.

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address decoding is now performed on the translated address which comes
from the memory mapper, instead of the address coming directly from the
cpu.

This means that you can access the full amount of ram at any address
that it is mapped to.
This commit is contained in:
Byron Lathi
2022-04-07 12:32:51 -05:00
parent 5548f9d02a
commit 2f79a00000
3 changed files with 17 additions and 17 deletions
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18
hw/fpga/addr_decode.sv
View File

@@ -1,5 +1,5 @@
module addr_decode(
input logic [15:0] addr,
input logic [23:0] addr,
output logic sdram_cs,
output logic rom_cs,
output logic hex_cs,
@@ -10,13 +10,13 @@ module addr_decode(
output logic mm_cs2
);
assign rom_cs = addr >= 16'h8000;
assign sdram_cs = addr < 16'h7fe0;
assign mm_cs1 = addr >= 16'h7fe0 && addr < 16'h7ff0;
assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff4;
assign uart_cs = addr >= 16'h7ff4 && addr < 16'h7ff6;
assign board_io_cs = addr == 16'h7ff6;
assign mm_cs2 = addr == 16'h7ff7;
assign irq_cs = addr == 16'h7fff;
assign rom_cs = addr >= 24'h008000 && addr < 24'h010000;
assign sdram_cs = addr < 24'h007fe0 || addr >= 24'h010000;
assign mm_cs1 = addr >= 24'h007fe0 && addr < 24'h007ff0;
assign hex_cs = addr >= 24'h007ff0 && addr < 24'h007ff4;
assign uart_cs = addr >= 24'h007ff4 && addr < 24'h007ff6;
assign board_io_cs = addr == 24'h007ff6;
assign mm_cs2 = addr == 24'h007ff7;
assign irq_cs = addr == 24'h007fff;
endmodule

8
hw/fpga/hvl/cs_testbench.sv
View File

@@ -4,7 +4,7 @@ timeunit 10ns;
timeprecision 1ns;
logic [15:0] addr;
logic [23:0] addr;
logic sdram_cs;
logic rom_cs;
logic hex_cs;
@@ -20,13 +20,13 @@ addr_decode dut(.*);
initial begin : TEST_VECTORS
for (int i = 0; i < 2**16; i++) begin
for (int i = 0; i < 2**24; i++) begin
addr <= i;
#1
assert(cs_count < 2)
else
$error("Multiple chip selects present!");
if (i < 16'h7fe0) begin
if (i < 16'h7fe0 || i >= 24'h010000) begin
assert(sdram_cs == '1)
else
$error("Bad CS! addr=%4x should have sdram_cs!", addr);
@@ -61,7 +61,7 @@ initial begin : TEST_VECTORS
else
$error("Bad CS! addr=%4x should have irq_cs!", addr);
end
if (i >= 2**15) begin
if (i >= 2**15 && i < 24'h010000) begin
assert(rom_cs == '1)
else
$error("Bad CS! addr=%4x should have rom_cs!", addr);

8
hw/fpga/super6502.sv
View File

@@ -89,8 +89,8 @@ assign cpu_irqb = irq_data_out == 0;
logic [11:0] mm_MO;
logic [23:0] mm_address;
assign mm_address = {mm_MO, cpu_addr[11:0]};
logic [23:0] mm_addr;
assign mm_addr = {mm_MO, cpu_addr[11:0]};
memory_mapper memory_mapper(
.clk(clk),
@@ -106,7 +106,7 @@ memory_mapper memory_mapper(
);
addr_decode decode(
.addr(cpu_addr),
.addr(mm_addr),
.sdram_cs(sdram_cs),
.rom_cs(rom_cs),
.hex_cs(hex_cs),
@@ -140,7 +140,7 @@ sdram sdram(
.rst(rst),
.clk_50(clk_50),
.cpu_clk(cpu_phi2),
.addr(mm_address),
.addr(mm_addr),
.sdram_cs(sdram_cs),
.rwb(cpu_rwb),
.data_in(cpu_data_in),