Add interrupt based timer and test code

hw/efinix_fpga/test_programs/Makefile

@@ -1,11 +1,18 @@
-TARGETS=stacktest runram timer
+TARGETS=stacktest runram timer timer_irq
+SRC=$(wildcard *.s)
+DIR=../ip/bram
 
 all: $(TARGETS)
 
-$(TARGETS):
+$(TARGETS): $(SRC)
 	cl65 --cpu 65c02 -C link.ld -l $@.list $@.s
 	xxd -ps $@ | fold -w 2 > $@.hex
 
+install:
+	cp $(TARGET).hex $(DIR)/init_hex.mem
+	cd $(DIR);python3 efx_mem_init_script.py hex init_hex.mem
+
+
 clean:
 	rm -f $(TARGETS)
 	rm *.hex

hw/efinix_fpga/test_programs/timer.s

@@ -2,13 +2,21 @@
 
 LEDS = $efff
 TIMER_BASE = $eff8
-TIMER_DIVISOR = 5
-
+TIMER_DIVISOR = 2
+TIMER_CL = 0
+TIMER_LL = 0
+TIMER_CH = 1
+TIMER_LH = 1
+TIMER_STATUS = 3
 TIMER_OLD = $10
 
 main:
-    lda #$ff
+    lda #$01
     sta TIMER_BASE+TIMER_DIVISOR
+    lda #$00
+    sta TIMER_BASE+TIMER_LH
+    lda #$0F
+    sta TIMER_BASE+TIMER_LL
     lda TIMER_BASE
     sta TIMER_OLD
     stz LEDS

hw/efinix_fpga/test_programs/timer_irq.s

@@ -0,0 +1,39 @@
+.code
+
+LEDS = $efff
+TIMER_BASE = $eff8
+TIMER_DIVISOR = 2
+TIMER_CL = 0
+TIMER_LL = 0
+TIMER_CH = 1
+TIMER_LH = 1
+TIMER_STATUS = 3
+TIMER_CONTROL = 3
+TIMER_OLD = $10
+
+main:
+    lda #$ff
+    sta TIMER_BASE+TIMER_DIVISOR
+    lda #$01
+    sta TIMER_BASE+TIMER_CONTROL
+    lda #$00
+    sta TIMER_BASE+TIMER_LH
+    lda #$10
+    sta TIMER_BASE+TIMER_LL
+    cli
+
+loop:
+    wai
+    bra loop
+
+irq:
+    lda TIMER_BASE
+    inc LEDS
+    rti
+
+    
+.segment "VECTORS"
+
+.addr main
+.addr main
+.addr irq