Add jsr test

hw/efinix_fpga/simulation/src/sim_top.sv

@@ -38,9 +38,9 @@ initial begin
     end
 end
 
-initial begin
-    #275000 $finish();
-end
+// initial begin
+//     #275000 $finish();
+// end
 
 initial begin
     $dumpfile("sim_top.vcd");

sw/Makefile

@@ -17,6 +17,6 @@ kernel:
 
 
 clean:
-	@$(MAKE) -C bootloader  --no-print-directory $@
+	@$(MAKE) -C bios  --no-print-directory $@
 	@$(MAKE) -C kernel  --no-print-directory $@
-	@$(MAKE) -C cc65  --no-print-directory $@
+	@$(MAKE) -C cc65  --no-print-directory $@

sw/test_code/jsr_test/Makefile

@@ -0,0 +1,39 @@
+CC=../../cc65/bin/cl65
+LD=../../cc65/bin/cl65
+CFLAGS=-T -t none -I. --cpu "65C02"
+LDFLAGS=-C link.ld -m $(NAME).map
+
+NAME=jsr_test
+
+BIN=$(NAME).bin
+HEX=$(NAME).hex
+
+LISTS=lists
+
+SRCS=$(wildcard *.s) $(wildcard *.c)
+SRCS+=$(wildcard **/*.s) $(wildcard **/*.c)
+OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS)))
+OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
+
+# Make sure the kernel linked to correct address, no relocation!
+all: $(HEX)
+
+$(HEX): $(BIN)
+	objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX)
+
+$(BIN): $(OBJS)
+	$(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@
+
+%.o: %.c $(LISTS)
+	$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
+
+%.o: %.s $(LISTS)
+	$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
+
+$(LISTS):
+	mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS))))
+
+.PHONY: clean
+clean:
+	rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map
+

sw/test_code/jsr_test/link.ld

@@ -0,0 +1,35 @@
+MEMORY
+{
+  ZP:  start = $0,    size = $100,  type = rw, define = yes;
+  SDRAM: start = $9200, size = $4d00, type = rw, define = yes;
+  ROM: start = $F000, size = $1000, file = %O;
+}
+
+SEGMENTS {
+    ZEROPAGE: load = ZP,  type = zp,  define   = yes;
+    DATA:     load = ROM, type = rw,  define   = yes, run = SDRAM;
+    BSS:      load = SDRAM, type = bss, define   = yes;
+    HEAP:     load = SDRAM, type = bss, optional = yes;
+    STARTUP:  load = ROM, type = ro;
+    ONCE:     load = ROM, type = ro,  optional = yes;
+    CODE:     load = ROM, type = ro;
+    RODATA:   load = ROM, type = ro;
+    VECTORS:  load = ROM, type = ro,  start    = $FFFA;
+}
+
+FEATURES {
+    CONDES:    segment = STARTUP,
+               type    = constructor,
+               label   = __CONSTRUCTOR_TABLE__,
+               count   = __CONSTRUCTOR_COUNT__;
+    CONDES:    segment = STARTUP,
+               type    = destructor,
+               label   = __DESTRUCTOR_TABLE__,
+               count   = __DESTRUCTOR_COUNT__;
+}
+
+SYMBOLS {
+    # Define the stack size for the application
+    __STACKSIZE__:  value = $0200, type = weak;
+    __STACKSTART__: type = weak, value = $0800; # 2k stack
+}

sw/test_code/jsr_test/main.s

@@ -0,0 +1,23 @@
+.export _init, _nmi_int, _irq_int
+
+.code
+
+_nmi_int:
+_irq_int:
+
+_init:
+    ldx #$ff
+    txs
+    lda #$00
+    jsr subroutine
+    sta $00
+@1: bra @1
+
+subroutine:
+    inc
+    jsr suborutine2
+    rts
+
+suborutine2:
+    inc
+    rts

sw/test_code/jsr_test/vectors.s

@@ -0,0 +1,14 @@
+; ---------------------------------------------------------------------------
+; vectors.s
+; ---------------------------------------------------------------------------
+;
+; Defines the interrupt vector table.
+
+.import    _init
+.import    _nmi_int, _irq_int
+
+.segment  "VECTORS"
+
+.addr      _nmi_int    ; NMI vector
+.addr      _init       ; Reset vector
+.addr      _irq_int    ; IRQ/BRK vector