Add jsr test

2023-10-15 13:30:09 -07:00
parent afd8de92cc
commit 32f6c0f8d9
6 changed files with 116 additions and 5 deletions
--- a/hw/efinix_fpga/simulation/src/sim_top.sv
+++ b/hw/efinix_fpga/simulation/src/sim_top.sv
@@ -38,9 +38,9 @@ initial begin
    end
 end

-initial begin
-    #275000 $finish();
-end
+// initial begin
+//     #275000 $finish();
+// end

 initial begin
    $dumpfile("sim_top.vcd");