Run simulation with verilog sd emulator

This also slowed the cpu clock down, we should speed it up again

hw/super6502_fpga/src/sim/hvl/sim_top.sv

@@ -39,7 +39,7 @@ initial begin
     clk_cpu <= '1;
     forever begin
         // #62.5 clk_cpu <= ~clk_cpu;
-        #250 clk_cpu <= ~clk_cpu;
+        #500 clk_cpu <= ~clk_cpu;
     end
 end
 

hw/super6502_fpga/src/sim/sources.list

@@ -3,4 +3,5 @@ sub/verilog-6502/ALU.v
 sub/verilog-6502/cpu_65c02.v
 sub/sim_sdram/generic_sdr.v
 sub/verilog-sd-emulator/src/sd_card_command.sv
-sub/verilog-sd-emulator/src/sd_card_emu.sv
+sub/verilog-sd-emulator/src/sd_card_emu.sv
+sub/verilog-sd-emulator/src/sd_card_state_controller.sv

hw/super6502_fpga/src/sub/cpu_wrapper/cpu_wrapper.sv

@@ -207,7 +207,7 @@ always @(posedge i_clk_100 or posedge i_rst) begin
     end 
 end
 
-localparam MAX_DELAY = 4;
+localparam MAX_DELAY = 8;
 
 logic [7:0] cycle_counter;
 logic too_late;