Run simulation with verilog sd emulator

This also slowed the cpu clock down, we should speed it up again
2024-03-14 08:17:05 -07:00
parent 24a7001aee
commit 335f877d66
6 changed files with 30 additions and 47 deletions
--- a/hw/super6502_fpga/src/sim/hvl/sim_top.sv
+++ b/hw/super6502_fpga/src/sim/hvl/sim_top.sv
@@ -39,7 +39,7 @@ initial begin
    clk_cpu <= '1;
    forever begin
        // #62.5 clk_cpu <= ~clk_cpu;
-        #250 clk_cpu <= ~clk_cpu;
+        #500 clk_cpu <= ~clk_cpu;
    end
 end