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Run simulation with verilog sd emulator

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This also slowed the cpu clock down, we should speed it up again
This commit is contained in:
Byron Lathi
2024-03-14 08:17:05 -07:00
parent 24a7001aee
commit 335f877d66
6 changed files with 30 additions and 47 deletions
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2
hw/super6502_fpga/src/sim/hvl/sim_top.sv
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@@ -39,7 +39,7 @@ initial begin
clk_cpu <= '1; clk_cpu <= '1;
forever begin forever begin
// #62.5 clk_cpu <= ~clk_cpu; // #62.5 clk_cpu <= ~clk_cpu;
#250 clk_cpu <= ~clk_cpu; #500 clk_cpu <= ~clk_cpu;
end end
end end

3
hw/super6502_fpga/src/sim/sources.list
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@@ -3,4 +3,5 @@ sub/verilog-6502/ALU.v
sub/verilog-6502/cpu_65c02.v sub/verilog-6502/cpu_65c02.v
sub/sim_sdram/generic_sdr.v sub/sim_sdram/generic_sdr.v
sub/verilog-sd-emulator/src/sd_card_command.sv sub/verilog-sd-emulator/src/sd_card_command.sv
sub/verilog-sd-emulator/src/sd_card_emu.sv sub/verilog-sd-emulator/src/sd_card_emu.sv
sub/verilog-sd-emulator/src/sd_card_state_controller.sv

2
hw/super6502_fpga/src/sim/sub/verilog-sd-emulator

Submodule hw/super6502_fpga/src/sim/sub/verilog-sd-emulator updated: 35c74ed8d7...5413066bbb

2
hw/super6502_fpga/src/sub/cpu_wrapper/cpu_wrapper.sv
View File

@@ -207,7 +207,7 @@ always @(posedge i_clk_100 or posedge i_rst) begin
end end
end end
localparam MAX_DELAY = 4; localparam MAX_DELAY = 8;
logic [7:0] cycle_counter; logic [7:0] cycle_counter;
logic too_late; logic too_late;

2
hw/super6502_fpga/src/sub/rtl-common

Submodule hw/super6502_fpga/src/sub/rtl-common updated: bb214bc79e...28da839bf6

66
sw/test_code/sd_controller_test/main.s
View File

@@ -20,6 +20,9 @@ _nmi_int:
_irq_int: _irq_int:
_init: _init:
ldx #$ff
txs
lda #$00 lda #$00
sta SD_CONTROLLER sta SD_CONTROLLER
@@ -32,21 +35,21 @@ _init:
sta SD_ARG+3 sta SD_ARG+3
lda #$08 lda #$08
sta SD_CONTROLLER sta SD_CONTROLLER
nop jsr delay
nop
nop
lda #55 lda #55
sta SD_CONTROLLER sta SD_CONTROLLER
jsr delay
lda #41 lda #41
sta SD_CONTROLLER sta SD_CONTROLLER
nop jsr delay
nop
nop
@acmd41: @acmd41:
lda #55 lda #55
sta SD_CONTROLLER sta SD_CONTROLLER
jsr delay
lda #$80 lda #$80
sta SD_ARG+1 sta SD_ARG+1
lda #$ff lda #$ff
@@ -56,11 +59,7 @@ _init:
lda #41 lda #41
sta SD_CONTROLLER sta SD_CONTROLLER
nop jsr delay
nop
nop
nop
nop
lda SD_RESP+3 lda SD_RESP+3
bmi card_ready bmi card_ready
@@ -76,30 +75,12 @@ card_ready:
lda #2 lda #2
sta SD_CONTROLLER sta SD_CONTROLLER
nop jsr delay
nop
nop
nop
nop
nop
nop
nop
nop
nop
lda #3 lda #3
sta SD_CONTROLLER sta SD_CONTROLLER
nop jsr delay
nop
nop
nop
nop
nop
nop
nop
nop
nop
lda SD_RESP lda SD_RESP
sta rca sta rca
@@ -121,18 +102,19 @@ card_ready:
lda #7 lda #7
sta SD_CONTROLLER sta SD_CONTROLLER
nop jsr delay
nop
nop
nop
nop
nop
nop
nop
nop
nop
lda #17 lda #17
sta SD_CONTROLLER sta SD_CONTROLLER
@end: bra @end @end: bra @end
delay:
nop
nop
nop
nop
nop
nop
nop
rts