Get the FPGA part working

This changes some of the clocks, fixes a bug in the seven segment stuff.
2022-03-11 22:55:26 -06:00
parent cdf3da9b13
commit 3d9d340520
11 changed files with 64714 additions and 11632 deletions
--- a/hw/fpga/SevenSeg.sv
+++ b/hw/fpga/SevenSeg.sv
@@ -16,7 +16,7 @@ logic [7:0] _data [2];
 always_ff @(posedge clk) begin
    if (rst)
        _data = '{default:'0};
-    if (~rw)
+    if (~rw & cs)
        _data[addr] <= data;
 end