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M2S a TCP

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This commit is contained in:
Byron Lathi
2024-09-21 19:17:13 -07:00
parent 8cb7281116
commit 404ad72b20
7 changed files with 119 additions and 38 deletions
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5
.gitmodules vendored
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@@ -21,4 +21,7 @@
url = ../stream_dmas.git
[submodule "hw/super6502_fpga/src/sub/interfaces"]
path = hw/super6502_fpga/src/sub/interfaces
url = ../interfaces.git
url = ../interfaces.git
[submodule "hw/super6502_fpga/src/sub/my-fifos"]
path = hw/super6502_fpga/src/sub/my-fifos
url = ../my-fifos.git

3
hw/super6502_fpga/sources.list
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@@ -7,4 +7,5 @@ src/sub/rtl-common/sources.list
src/sub/sd_controller_wrapper/sources.list
src/sub/wb2axip/sources.list
src/sub/verilog-ethernet/sources.list
src/sub/stream_dmas/sources.list
src/sub/stream_dmas/sources.list
src/sub/my-fifos/sources.list

1
hw/super6502_fpga/src/sub/my-fifos Submodule

Submodule hw/super6502_fpga/src/sub/my-fifos added at a19156c9cd

39
hw/super6502_fpga/src/sub/network_processor/sim/cocotb/tests/tcp_test.py
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@@ -175,4 +175,41 @@ async def test_simple(dut):
tb.log.info(f"window: {tcp_packet.window}")
tb.log.info(f"Checksum: {tcp_packet.chksum}")
assert tcp_packet.ack == tb_seq + 1
assert tcp_packet.ack == tb_seq + 1
# Try to send a packet from M2S
# Construct a descriptor in memry
tb.axil_ram.write_dword(0x00000000, 0x00001000)
tb.axil_ram.write_dword(0x00000004, 64)
tb.axil_ram.write_dword(0x00000008, 0)
tb.axil_ram.write_dword(0x0000000c, 0)
test_data = bytearray([x % 256 for x in range(256)])
tb.axil_ram.write(0x1000, test_data)
await tb.axil_master.write_dword(0x22c, 0)
await tb.axil_master.write_dword(0x220, 0x00000000)
await tb.axil_master.write_dword(0x224, 0x00000000)
resp = await tb.mii_phy.tx.recv() # type: GmiiFrame
packet = Ether(resp.get_payload())
pktdump.write(packet)
tb.log.info(f"Packet Type: {packet.type:x}")
tcp_packet = ip_packet.payload
assert isinstance(tcp_packet, TCP)
tb.log.info(f"Source Port: {tcp_packet.sport}")
tb.log.info(f"Dest Port: {tcp_packet.dport}")
tb.log.info(f"Seq: {tcp_packet.seq}")
tb.log.info(f"Ack: {tcp_packet.ack}")
tb.log.info(f"Data Offs: {tcp_packet.dataofs}")
tb.log.info(f"flags: {tcp_packet.flags}")
tb.log.info(f"window: {tcp_packet.window}")
tb.log.info(f"Checksum: {tcp_packet.chksum}")
pktdump.close()

19
hw/super6502_fpga/src/sub/network_processor/src/tcp_packet_generator.sv
View File

@@ -127,19 +127,36 @@ always_comb begin
18: m_ip.ip_payload_axis_tdata = '0;
19: begin
m_ip.ip_payload_axis_tdata = '0;
m_ip.ip_payload_axis_tlast = '1;
m_ip.ip_payload_axis_tlast = ~s_axis_data.tvalid; // kinda hacky
end
endcase
if (m_ip.ip_payload_axis_tready) begin
counter_next = counter + 1;
if (counter == 19) begin
state_next = DATA;
end
if (m_ip.ip_payload_axis_tlast) begin
state_next = IDLE;
o_packet_done = '1;
end
end
end
DATA: begin
state_next = DATA;
s_axis_data.tready = m_ip.ip_payload_axis_tready;
m_ip.ip_payload_axis_tvalid = s_axis_data.tvalid;
m_ip.ip_payload_axis_tdata = s_axis_data.tdata;
m_ip.ip_payload_axis_tlast = s_axis_data.tlast;
if (s_axis_data.tlast && s_axis_data.tvalid && s_axis_data.tready) begin
state_next = IDLE;
o_packet_done = '1;
end
end
endcase
end

56
hw/super6502_fpga/src/sub/network_processor/src/tcp_stream.sv
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@@ -35,6 +35,8 @@ axis_intf s2m_axis();
axis_intf m2s_post_saf_axis();
axis_intf s2m_pre_saf_axis();
axis_intf m_tx_ctrl_axis_data();
// regs
tcp_stream_regs_pkg::tcp_stream_regs__in_t hwif_in;
tcp_stream_regs_pkg::tcp_stream_regs__out_t hwif_out;
@@ -47,6 +49,7 @@ tcp_pkg::rx_msg_t rx_msg;
logic rx_msg_valid;
logic rx_msg_ack;
logic [15:0] w_saf_pkt_len;
logic [15:0] w_tx_ip_len;
logic [31:0] w_tx_seq_number;
logic [31:0] w_tx_ack_number;
@@ -133,42 +136,27 @@ tcp_state_manager u_tcp_state_manager (
// tx buffer
axis_fifo #(
.DEPTH(4096),
.DATA_WIDTH(DATA_WIDTH),
.FRAME_FIFO(1)
axis_saf_fifo #(
.DATA_DEPTH_L2(12),
.CTRL_DEPTH_L2(7),
.DATA_MEM("distributed"),
.CTRL_MEM("distributed")
) m2s_saf_fifo (
.clk (clk),
.rst (rst),
.sclk (clk),
.srst (rst),
.s_axis (m2s_axis),
.s_axis_tdata (m2s_axis.tdata),
.s_axis_tkeep (m2s_axis.tkeep),
.s_axis_tvalid (m2s_axis.tvalid),
.s_axis_tready (m2s_axis.tready),
.s_axis_tlast (m2s_axis.tlast),
.s_axis_tid (m2s_axis.tid),
.s_axis_tdest (m2s_axis.tdest),
.s_axis_tuser (m2s_axis.tuser),
.mclk (clk),
.mrst (rst),
.m_axis (m2s_post_saf_axis),
.m_axis_tdata (m2s_post_saf_axis.tdata),
.m_axis_tkeep (m2s_post_saf_axis.tkeep),
.m_axis_tvalid (m2s_post_saf_axis.tvalid),
.m_axis_tready (m2s_post_saf_axis.tready),
.m_axis_tlast (m2s_post_saf_axis.tlast),
.m_axis_tid (m2s_post_saf_axis.tid),
.m_axis_tdest (m2s_post_saf_axis.tdest),
.m_axis_tuser (m2s_post_saf_axis.tuser),
.pause_req ('0),
.pause_ack (),
.status_depth (),
.status_depth_commit (),
.status_overflow (),
.status_bad_frame (),
.status_good_frame ()
.o_len (w_saf_pkt_len),
.o_rx_pkt (),
.o_tx_pkt (),
.o_drop ()
);
// tx control
tcp_tx_ctrl u_tcp_tx_ctrl (
.i_clk (clk),
@@ -185,6 +173,10 @@ tcp_tx_ctrl u_tcp_tx_ctrl (
.o_window_size (w_tx_window_size),
.o_hdr_valid (w_tx_hdr_valid),
.s_axis_len (w_saf_pkt_len),
.s_axis (m2s_post_saf_axis),
.m_axis (m_tx_ctrl_axis_data),
.i_packet_done (w_tx_packet_done)
);
@@ -193,7 +185,7 @@ tcp_packet_generator u_tcp_packet_generator (
.i_clk (clk),
.i_rst (rst),
.s_axis_data (m2s_post_saf_axis),
.s_axis_data (m_tx_ctrl_axis_data),
.i_ip_len (w_tx_ip_len),
.i_seq_number (w_tx_seq_number),

34
hw/super6502_fpga/src/sub/network_processor/src/tcp_tx_ctrl.sv
View File

@@ -15,9 +15,22 @@ module tcp_tx_ctrl(
output logic [15:0] o_window_size,
output logic o_hdr_valid,
axis_intf.SLAVE s_axis,
input logic [15:0] s_axis_len,
axis_intf.MASTER m_axis,
input wire i_packet_done
);
assign m_axis.tdata = s_axis.tdata;
assign m_axis.tkeep = s_axis.tkeep;
assign m_axis.tvalid = s_axis.tvalid;
assign s_axis.tready = m_axis.tready;
assign m_axis.tlast = s_axis.tlast;
assign m_axis.tid = s_axis.tid;
assign m_axis.tdest = s_axis.tdest;
assign m_axis.tuser = s_axis.tuser;
localparam FLAG_FIN = (1 << 0);
localparam FLAG_SYN = (1 << 1);
localparam FLAG_RST = (1 << 2);
@@ -30,7 +43,7 @@ localparam FLAG_CWR = (1 << 7);
logic [31:0] seq_num, seq_num_next;
assign o_seq_number = seq_num;
enum logic [2:0] {IDLE, SEND_SYN, SEND_ACK} state, state_next;
enum logic [2:0] {IDLE, SEND_SYN, SEND_ACK, SEND_DATA} state, state_next;
always_ff @(posedge i_clk) begin
if (i_rst) begin
@@ -43,6 +56,8 @@ always_ff @(posedge i_clk) begin
end
always_comb begin
state_next = state;
o_ack_number = '0;
o_flags = '0;
o_window_size = 16'b1;
@@ -62,6 +77,10 @@ always_comb begin
TX_CTRL_SEND_ACK: state_next = SEND_ACK;
endcase
end
if (s_axis.tvalid) begin
state_next = SEND_DATA;
end
end
SEND_SYN: begin
@@ -80,7 +99,18 @@ always_comb begin
if (i_packet_done) begin
state_next = IDLE;
seq_num_next = seq_num + 1;
seq_num_next = seq_num;
end
end
SEND_DATA: begin
o_flags = FLAG_ACK;
o_ip_len = 16'd40 + s_axis_len; // default length of IP packet
o_hdr_valid = '1;
if (i_packet_done) begin
state_next = IDLE;
seq_num_next = seq_num + s_axis_len;
end
end
endcase