Add multiplier

Add 16x16 multiplier.

Pretty simple. Address 0-1 is multipled by address 2-3 and the result is
in address 4-7, all little endian of course.

hw/efinix_fpga/addr_decode.sv

@@ -5,12 +5,14 @@ module addr_decode
     output o_rom_cs,
     output o_leds_cs,
     output o_timer_cs,
+    output o_multiplier_cs,
     output o_sdram_cs
 );
 
 assign o_rom_cs = i_addr >= 16'hf000 && i_addr <= 16'hffff;
-assign o_leds_cs = i_addr == 16'hefff;
 assign o_timer_cs = i_addr >= 16'heff8 && i_addr <= 16'heffb;
+assign o_multiplier_cs = i_addr >= 16'heff0 && i_addr <= 16'heff7;
+assign o_leds_cs = i_addr == 16'hefff;
 assign o_sdram_cs = i_addr < 16'h8000;
 
 endmodule

hw/efinix_fpga/debug_profile.wizard.json

@@ -3,7 +3,7 @@
         {
             "name": "la0",
             "type": "la",
-            "uuid": "281a52604f2c437c9bde96b89d672260",
+            "uuid": "aad3ac84df754229b9f34a0d7163d7ac",
             "trigin_en": false,
             "trigout_en": false,
             "auto_inserted": true,

hw/efinix_fpga/ip/bram/bram_ini.vh

@@ -4,9 +4,9 @@ input integer index;//Mode type
 input integer val_; //Port A index, Port B Index, Number of Items in Loop, Port A Start, Port B Start, reserved 
 case (index)
    0: bram_ini_table=
-(val_== 0)?256'h008d00000000a9000ef000fb0008d00001000a9000ef000fa0008d000ff000a9:
-(val_== 1)?256'h0f8000ad000fd00080000cb00058000ef000f80008d00010000a9000ef000f90:
-(val_== 2)?256'h000000000000000000000000000000000000000040000ef000ff000ee000ef00:
+(val_== 0)?256'h008d000c8000a9000ef000f10008d00000000a9000ef000f00008d0007b000a9:
+(val_== 1)?256'h0ef000ff0008d000ef000f5000ad000ef000f30008d00001000a9000ef000f20:
+(val_== 2)?256'h00000000000000000000000000000000000000000000000000e300080000cb00:
 (val_== 3)?256'h0000000000000000000000000000000000000000000000000000000000000000:
 (val_== 4)?256'h0000000000000000000000000000000000000000000000000000000000000000:
 (val_== 5)?256'h0000000000000000000000000000000000000000000000000000000000000000:
@@ -23,7 +23,7 @@ case (index)
 (val_==16)?256'h0000000000000000000000000000000000000000000000000000000000000000:
 (val_==17)?256'h0000000000000000000000000000000000000000000000000000000000000000:
 (val_==18)?256'h0000000000000000000000000000000000000000000000000000000000000000:
-(val_==19)?256'h000ff00018000ff00000000ff000000000000000000000000000000000000000:
+(val_==19)?256'h000ff00000000ff00000000ff000000000000000000000000000000000000000:
 (val_==20)?256'h0000000000000000000000000000000000000000000000000000000000000000:
 (val_==21)?256'h0000000000000000000000000000000000000000000000000000000000000000:
 (val_==22)?256'h0000000000000000000000000000000000000000000000000000000000000000:

hw/efinix_fpga/ip/bram/init_hex.mem

@@ -1,34 +1,34 @@
 a9
-ff
+7b
 8d
-fa
+f0
+ef
+a9
+00
+8d
+f1
+ef
+a9
+c8
+8d
+f2
 ef
 a9
 01
 8d
-fb
+f3
+ef
+ad
+f5
 ef
-a9
-00
 8d
-f9
+ff
 ef
-a9
-10
-8d
-f8
-ef
-58
 cb
 80
-fd
-ad
-f8
-ef
-ee
-ff
-ef
-40
+e3
+00
+00
 00
 00
 00
@@ -252,5 +252,5 @@ ef
 ff
 00
 ff
-18
+00
 ff

hw/efinix_fpga/multiplier.sv

@@ -0,0 +1,46 @@
+module multiplier(
+    input clk,
+    input reset,
+    input [7:0] i_data,
+    output logic [7:0] o_data,
+    input cs,
+    input rwb,
+    input [2:0] addr
+);
+
+logic [15:0] a, b;
+logic [31:0] out;
+
+always_ff @(negedge clk) begin
+    if (reset) begin
+        a <= '0;
+        b <= '0;
+    end
+
+
+    if (cs & ~rwb) begin
+        case (addr)
+            3'h0: begin
+                a[7:0] <= i_data;
+            end
+
+            3'h1: begin
+                a[15:8] <= i_data;
+            end
+
+            3'h2: begin
+                b[7:0] <= i_data;
+            end
+
+            3'h3: begin
+                b[15:8] <= i_data;
+            end
+        endcase
+    end
+end
+
+assign out = a * b;
+assign o_data = out[((addr-4)*8)+:8];
+
+
+endmodule

hw/efinix_fpga/super6502.sv

@@ -66,18 +66,21 @@ logic w_rom_cs;
 logic w_leds_cs;
 logic w_sdram_cs;
 logic w_timer_cs;
+logic w_multiplier_cs;
 
 addr_decode u_addr_decode(
     .i_addr(cpu_addr),
     .o_rom_cs(w_rom_cs),
     .o_leds_cs(w_leds_cs),
     .o_timer_cs(w_timer_cs),
+    .o_multiplier_cs(w_multiplier_cs),
     .o_sdram_cs(w_sdram_cs)
 );
 
 logic [7:0] w_rom_data_out;
 logic [7:0] w_leds_data_out;
 logic [7:0] w_timer_data_out;
+logic [7:0] w_multiplier_data_out;
 logic [7:0] w_sdram_data_out;
 
 always_comb begin
@@ -87,6 +90,8 @@ always_comb begin
         cpu_data_out = w_leds_data_out;
     else if (w_timer_cs)
         cpu_data_out = w_timer_data_out;
+    else if (w_multiplier_cs)
+        cpu_data_out = w_multiplier_data_out;
     else if (w_sdram_cs)
         cpu_data_out = w_sdram_data_out;
     else
@@ -127,6 +132,16 @@ timer u_timer(
     .irqb(w_timer_irqb)
 );
 
+multiplier u_multiplier(
+    .clk(clk_2),
+    .reset(~cpu_resb),
+    .i_data(cpu_data_in),
+    .o_data(w_multiplier_data_out),
+    .cs(w_multiplier_cs),
+    .rwb(cpu_rwb),
+    .addr(cpu_addr[2:0])
+);
+
 sdram_adapter u_sdram_adapter(
     .i_cpuclk(clk_2),
     .i_arst(~button_reset),

hw/efinix_fpga/super6502.xml

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<efx:project name="super6502" description="" last_change_date="Tue January 3 2023 18:18:26" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project name="super6502" description="" last_change_date="Wed January 4 2023 15:54:48" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion"/>
         <efx:device name="T20F256"/>
@@ -18,6 +18,7 @@
         <efx:design_file name="sdram_adapter.sv" version="default" library="default"/>
         <efx:design_file name="timer.sv" version="default" library="default"/>
         <efx:design_file name="interrupt_controller.sv" version="default" library="default"/>
+        <efx:design_file name="multiplier.sv" version="default" library="default"/>
         <efx:top_vhdl_arch name=""/>
     </efx:design_info>
     <efx:constraint_info>
@@ -88,7 +89,7 @@
     </efx:bitstream_generation>
     <efx:debugger>
         <efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
-        <efx:param name="auto_instantiation" value="on" value_type="e_bool"/>
+        <efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
         <efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string"/>
     </efx:debugger>
 </efx:project>

hw/efinix_fpga/test_programs/Makefile

@@ -1,4 +1,4 @@
-TARGETS=stacktest runram timer timer_irq
+TARGETS=stacktest runram timer timer_irq multiplier
 SRC=$(wildcard *.s)
 DIR=../ip/bram
 

hw/efinix_fpga/test_programs/multiplier.s

@@ -0,0 +1,32 @@
+.code
+
+LEDS = $efff
+MULTAL = $eff0
+MULTAH = $eff1
+MULTBL = $eff2
+MULTBH = $eff3
+
+MULTPLL = $eff4
+MULTPLH = $eff5
+MULTPHL = $eff6
+MULTPHH = $eff7
+
+main:
+    lda #$7b
+    sta MULTAL
+    lda #$00
+    sta MULTAH
+    lda #$c8
+    sta MULTBL
+    lda #$01
+    sta MULTBH
+    lda MULTPLH
+    sta LEDS
+    wai
+    bra main
+
+.segment "VECTORS"
+
+.addr main
+.addr main
+.addr main