Add test code and top level Makefile

.gitmodules

@@ -4,3 +4,6 @@
 [submodule "hw/super6502_fpga/src/sub/axi_crossbar"]
 	path = hw/super6502_fpga/src/sub/axi_crossbar
 	url = ../axi_crossbar.git
+[submodule "sw/toolchain/cc65"]
+	path = sw/toolchain/cc65
+	url = ../cc65.git

Makefile

@@ -1,9 +1,32 @@
-all: hw
+ROM_TARGET=test_code/loop_test
 
-.PHONY: hw
+INIT_HEX=hw/super6502_fpga/init_hex.mem
-hw:
+HEX=sw/$(ROM_TARGET)/$(notdir $(ROM_TARGET)).bin
-	$(MAKE) -C hw
+
+
+all: fpga_image
+
+# FPGA
+.PHONY: fpga_image
+fpga_image: $(INIT_HEX)
+	$(MAKE) -C hw/super6502_fpga
+
+
+# SW
+.PHONY: toolchain
+toolchain:
+	$(MAKE) -C sw/toolchain/cc65 -j $(shell nproc)
+
+$(INIT_HEX): toolchain script/generate_rom_image.py $(HEX)
+	python script/generate_rom_image.py -i $(HEX) -o $@
+
+$(HEX):
+	$(MAKE) -C sw/$(ROM) $(notdir $@)
 
 .PHONY: clean
 clean:
-	$(MAKE) -C hw $@
+	$(MAKE) -C hw/super6502_fpga $@
+
+.PHONY: distclean
+distclean: clean
+	$(MAKE) -C sw/toolchain/cc65 clean

hw/Makefile

@@ -1,6 +0,0 @@
-all:
-	$(MAKE) -C super6502_fpga
-
-.PHONY: clean
-clean:
-	$(MAKE) -C super6502_fpga $@

hw/super6502_fpga/super6502_fpga.xml

@@ -1,4 +1,4 @@
-<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Sat Mar 02 2024 10:46:33 PM" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Sun Mar 03 2024 12:51:24 PM" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion" />
         <efx:device name="T20F256" />

script/generate_rom_image.py

@@ -0,0 +1,40 @@
+import getopt
+import sys
+
+# ROM size in bytes
+ROM_SIZE = 2**16
+DATA_WIDTH = 32
+
+NUM_ENTRIES = ROM_SIZE // (DATA_WIDTH//8)
+
+def main(argv):
+    inputfile = ''
+    outputfile = ''
+    opts, args = getopt.getopt(argv,"hi:o:",["ifile=","ofile="])
+    for opt, arg in opts:
+        if opt == '-h':
+            print ('test.py -i <inputfile> -o <outputfile>')
+            sys.exit()
+        elif opt in ("-i", "--ifile"):
+            inputfile = arg
+        elif opt in ("-o", "--ofile"):
+            outputfile = arg
+
+    with open(outputfile, "w") as init_file, open(inputfile, "rb") as hex_file:
+        init_file.write("@00000000\n")
+
+        while True:
+            hex_bytes = hex_file.read(4)
+            if len(hex_bytes) == 0:
+                break
+
+            val = int.from_bytes(hex_bytes, byteorder="little")
+            init_file.write(f"{val:x}\n")
+
+            if len(hex_bytes) < 4:
+                break
+        
+        print("Done!")
+
+if __name__ == "__main__":
+    main(sys.argv[1:])

sw/test_code/loop_test/Makefile

@@ -0,0 +1,39 @@
+CC=../../toolchain/cc65/bin/cl65
+LD=../../toolchain/cc65/bin/cl65
+CFLAGS=-T -t none -I. --cpu "65C02"
+LDFLAGS=-C link.ld -m $(NAME).map
+
+NAME=loop_test
+
+BIN=$(NAME).bin
+HEX=$(NAME).hex
+
+LISTS=lists
+
+SRCS=$(wildcard *.s) $(wildcard *.c)
+SRCS+=$(wildcard **/*.s) $(wildcard **/*.c)
+OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS)))
+OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
+
+# Make sure the kernel linked to correct address, no relocation!
+all: $(HEX)
+
+$(HEX): $(BIN)
+	objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX)
+
+$(BIN): $(OBJS)
+	$(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@
+
+%.o: %.c $(LISTS)
+	$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
+
+%.o: %.s $(LISTS)
+	$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
+
+$(LISTS):
+	mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS))))
+
+.PHONY: clean
+clean:
+	rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map
+

sw/test_code/loop_test/link.ld

@@ -0,0 +1,30 @@
+MEMORY
+{
+    RAM: start = $0000, size = $200;
+    ROM: start = $FF00, size = $100, file = %O;
+}
+
+SEGMENTS {
+    ZEROPAGE: load = RAM, type = zp,  define   = yes;
+    DATA:     load = ROM, type = rw,  define   = yes;
+    CODE:     load = ROM, type = ro;
+    RODATA:   load = ROM, type = ro;
+    VECTORS:  load = ROM, type = ro,  start    = $FFFA;
+}
+
+FEATURES {
+    CONDES:    segment = STARTUP,
+               type    = constructor,
+               label   = __CONSTRUCTOR_TABLE__,
+               count   = __CONSTRUCTOR_COUNT__;
+    CONDES:    segment = STARTUP,
+               type    = destructor,
+               label   = __DESTRUCTOR_TABLE__,
+               count   = __DESTRUCTOR_COUNT__;
+}
+
+SYMBOLS {
+    # Define the stack size for the application
+    __STACKSIZE__:  value = $0200, type = weak;
+    __STACKSTART__: type = weak, value = $0800; # 2k stack
+}

sw/test_code/loop_test/lists/main.s.list

@@ -0,0 +1,31 @@
+ca65 V2.19 - Git 71b58f796
+Main file   : main.s
+Current file: main.s
+
+000000r 1               .export _init, _nmi_int, _irq_int
+000000r 1               
+000000r 1               
+000000r 1               SDRAM = $200
+000000r 1               
+000000r 1               .segment  "VECTORS"
+000000r 1               
+000000r 1  rr rr        .addr      _nmi_int    ; NMI vector
+000002r 1  rr rr        .addr      _init       ; Reset vector
+000004r 1  rr rr        .addr      _irq_int    ; IRQ/BRK vector
+000006r 1               
+000006r 1               .code
+000000r 1               
+000000r 1               _nmi_int:
+000000r 1               _irq_int:
+000000r 1               
+000000r 1               _init:
+000000r 1  A9 00                lda #$00
+000002r 1               @start:
+000002r 1  8D 00 02             sta SDRAM
+000005r 1  CD 00 02             cmp SDRAM
+000008r 1  D0 03                bne @end
+00000Ar 1  1A                   ina
+00000Br 1  80 F5                bra @start
+00000Dr 1               
+00000Dr 1  80 FE        @end:   bra @end
+00000Dr 1               

sw/test_code/loop_test/loop_test.map

@@ -0,0 +1,28 @@
+Modules list:
+-------------
+main.o:
+    CODE              Offs=000000  Size=00000F  Align=00001  Fill=0000
+    VECTORS           Offs=000000  Size=000006  Align=00001  Fill=0000
+
+
+Segment list:
+-------------
+Name                   Start     End    Size  Align
+----------------------------------------------------
+CODE                  00FF00  00FF0E  00000F  00001
+VECTORS               00FFFA  00FFFF  000006  00001
+
+
+Exports list by name:
+---------------------
+
+
+
+Exports list by value:
+----------------------
+
+
+
+Imports list:
+-------------
+

sw/test_code/loop_test/main.s

@@ -0,0 +1,26 @@
+.export _init, _nmi_int, _irq_int
+
+.segment  "VECTORS"
+
+.addr      _nmi_int    ; NMI vector
+.addr      _init       ; Reset vector
+.addr      _irq_int    ; IRQ/BRK vector
+
+.zeropage
+tmp: .res 1
+
+.code
+
+_nmi_int:
+_irq_int:
+
+_init:
+        lda #$00
+@start:
+        sta tmp
+        cmp tmp
+        bne @end
+        ina
+        bra @start
+
+@end:   bra @end