Add uart2 test program

Reads input from uart and then writes it back out again immediately.

hw/efinix_fpga/debug_profile.wizard.json

@@ -3,7 +3,7 @@
         {
             "name": "la0",
             "type": "la",
-            "uuid": "c67ec8d558d3431ca6ca818984576c7b",
+            "uuid": "44caec2ec3a74324b8ff7cb201ab080b",
             "trigin_en": false,
             "trigout_en": false,
             "auto_inserted": true,

hw/efinix_fpga/ip/bram/bram_ini.vh

@@ -4,8 +4,8 @@ input integer index;//Mode type
 input integer val_; //Port A index, Port B Index, Number of Items in Loop, Port A Start, Port B Start, reserved 
 case (index)
    0: bram_ini_table=
-(val_== 0)?256'h006500048000fd00080000cb000ef000e60008d000ff0000b000bd00000000a2:
-(val_== 1)?256'h0000000000021000640006c000720006f00077000200002c0006f0006c0006c0:
+(val_== 0)?256'h008d000ef000e6000ad000f9000f00000100089000ef000e7000ad00000000a2:
+(val_== 1)?256'h0000000000000000000000000000000000000000000000f100080000ef000e60:
 (val_== 2)?256'h0000000000000000000000000000000000000000000000000000000000000000:
 (val_== 3)?256'h0000000000000000000000000000000000000000000000000000000000000000:
 (val_== 4)?256'h0000000000000000000000000000000000000000000000000000000000000000:

hw/efinix_fpga/ip/bram/init_hex.mem

@@ -1,27 +1,27 @@
 a2
 00
-bd
-0b
-ff
+ad
+e7
+ef
+89
+01
+f0
+f9
+ad
+e6
+ef
 8d
 e6
 ef
-cb
 80
-fd
-48
-65
-6c
-6c
-6f
-2c
-20
-77
-6f
-72
-6c
-64
-21
+f1
+00
+00
+00
+00
+00
+00
+00
 00
 00
 00

hw/efinix_fpga/super6502.xml

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<efx:project name="super6502" description="" last_change_date="Thu January 12 2023 12:02:15" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project name="super6502" description="" last_change_date="Thu January 12 2023 14:00:46" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion"/>
         <efx:device name="T20F256"/>

hw/efinix_fpga/test_programs/Makefile

@@ -1,4 +1,4 @@
-TARGETS=stacktest runram timer timer_irq multiplier divider uart
+TARGETS=stacktest runram timer timer_irq multiplier divider uart uart2
 SRC=$(wildcard *.s)
 DIR=../ip/bram
 

hw/efinix_fpga/test_programs/uart.s

@@ -9,7 +9,14 @@ main:
     ldx #$00
 loop:
     lda string,x
+    beq end
     sta UART_TX
+    inx
+wait:
+    lda UART_STATUS
+    bit #$02
+    beq loop
+    bra wait
 
 end:
     wai

hw/efinix_fpga/test_programs/uart2.s

@@ -0,0 +1,23 @@
+.code
+
+UART_TX = $efe6
+UART_RX = UART_TX
+UART_STATUS = $efe7
+UART_CONTROL = UART_STATUS
+
+main:
+    ldx #$00
+loop:
+    lda UART_STATUS ; see if bit 0 is set
+    bit #$01
+    beq loop
+    lda UART_RX     ; read rx buffer if so
+    sta UART_TX     ; transmit it back again
+    bra loop
+
+
+.segment "VECTORS"
+
+.addr main
+.addr main
+.addr main