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Get block rom kind of working

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This commit is contained in:
Byron Lathi
2022-12-20 15:38:55 -05:00
parent 19b13164e9
commit 52de8d3eb3
14 changed files with 8969 additions and 9 deletions
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134
hw/efinix_fpga/debug_profile.wizard.json
View File

@@ -3,12 +3,12 @@
{
"name": "la0",
"type": "la",
"uuid": "d0d972d74e3f4c45a9c473ba07318a8e",
"uuid": "2ec8ec3d274747939b82c28997a2ef1d",
"trigin_en": false,
"trigout_en": false,
"auto_inserted": true,
"capture_control": false,
"data_depth": 2048,
"data_depth": 128,
"input_pipeline": 1,
"probes": [
{
@@ -40,6 +40,21 @@
"name": "cpu_sync",
"width": 1,
"probe_type": 1
},
{
"name": "cpu_data_out",
"width": 8,
"probe_type": 1
},
{
"name": "cpu_data_oe",
"width": 8,
"probe_type": 1
},
{
"name": "cpu_phi2",
"width": 1,
"probe_type": 1
}
]
}
@@ -309,6 +324,91 @@
"name": "la0_probe5",
"net": "cpu_sync",
"path": []
},
{
"name": "la0_probe6[0]",
"net": "cpu_data_out[0]",
"path": []
},
{
"name": "la0_probe6[1]",
"net": "cpu_data_out[1]",
"path": []
},
{
"name": "la0_probe6[2]",
"net": "cpu_data_out[2]",
"path": []
},
{
"name": "la0_probe6[3]",
"net": "cpu_data_out[3]",
"path": []
},
{
"name": "la0_probe6[4]",
"net": "cpu_data_out[4]",
"path": []
},
{
"name": "la0_probe6[5]",
"net": "cpu_data_out[5]",
"path": []
},
{
"name": "la0_probe6[6]",
"net": "cpu_data_out[6]",
"path": []
},
{
"name": "la0_probe6[7]",
"net": "cpu_data_out[7]",
"path": []
},
{
"name": "la0_probe7[0]",
"net": "cpu_data_oe[0]",
"path": []
},
{
"name": "la0_probe7[1]",
"net": "cpu_data_oe[1]",
"path": []
},
{
"name": "la0_probe7[2]",
"net": "cpu_data_oe[2]",
"path": []
},
{
"name": "la0_probe7[3]",
"net": "cpu_data_oe[3]",
"path": []
},
{
"name": "la0_probe7[4]",
"net": "cpu_data_oe[4]",
"path": []
},
{
"name": "la0_probe7[5]",
"net": "cpu_data_oe[5]",
"path": []
},
{
"name": "la0_probe7[6]",
"net": "cpu_data_oe[6]",
"path": []
},
{
"name": "la0_probe7[7]",
"net": "cpu_data_oe[7]",
"path": []
},
{
"name": "la0_probe8",
"net": "cpu_phi2",
"path": []
}
]
}
@@ -322,7 +422,7 @@
],
"session": {
"wizard": {
"data_depth": 2048,
"data_depth": 128,
"capture_control": false,
"selected_nets": [
{
@@ -376,6 +476,34 @@
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": []
},
{
"name": "cpu_data_out",
"width": 8,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": [],
"net_idx_left": 7,
"net_idx_right": 0
},
{
"name": "cpu_data_oe",
"width": 8,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": [],
"net_idx_left": 7,
"net_idx_right": 0
},
{
"name": "cpu_phi2",
"width": 1,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": []
}
],
"top_module": "super6502",

111
hw/efinix_fpga/ip/bram/bram_decompose.vh Normal file
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@@ -0,0 +1,111 @@
localparam FAMILY = 0; //0:Trion, 1:Titanium
localparam ADDR_WIDTH_A = 8;
localparam DATA_WIDTH_A = 8;
localparam ADDR_WIDTH_B = 8;
localparam DATA_WIDTH_B = 8;
localparam TOTAL_SIZE_A = 256;
localparam TOTAL_SIZE_B = 256;
localparam BYTEEN_WIDTH = 1;
localparam BYTEEN_WIDTH_A = 1;
localparam BYTEEN_WIDTH_B = 1;
localparam GROUP_DATA_WIDTH = 8;
localparam GROUP_DATA_WIDTH_A = 0;
localparam GROUP_DATA_WIDTH_B = 0;
localparam GROUP_COLUMNS = 1;
localparam bram_table_size = 1;
localparam bram_table_loop_mode = 1;
localparam bram_mapping_size = 1;
localparam rMux_mapping_A_size = 0;
localparam rMux_mapping_B_size = 0;
localparam wen_sel_mapping_A_size = 0;
localparam wen_sel_mapping_B_size = 0;
localparam data_mapping_table_A_size = 0;
localparam data_mapping_table_B_size = 0;
localparam address_mapping_table_A_size = 0;
localparam address_mapping_table_B_size = 0;
function integer bram_feature_table;
input integer index;//Mode type
input integer val_; //Address_width, data_width, en_width, reserved
case (index)
0: bram_feature_table=(val_==0)?8:(val_==1)?20:(val_==2)?2:(val_==3)?0:(val_==4)?0:0;
1: bram_feature_table=(val_==0)?9:(val_==1)?10:(val_==2)?1:(val_==3)?0:(val_==4)?0:0;
2: bram_feature_table=(val_==0)?10:(val_==1)?5:(val_==2)?1:(val_==3)?0:(val_==4)?0:0;
3: bram_feature_table=(val_==0)?8:(val_==1)?16:(val_==2)?2:(val_==3)?0:(val_==4)?1:0;
4: bram_feature_table=(val_==0)?9:(val_==1)?8:(val_==2)?1:(val_==3)?0:(val_==4)?1:0;
5: bram_feature_table=(val_==0)?10:(val_==1)?4:(val_==2)?1:(val_==3)?0:(val_==4)?1:0;
6: bram_feature_table=(val_==0)?11:(val_==1)?2:(val_==2)?1:(val_==3)?0:(val_==4)?1:0;
7: bram_feature_table=(val_==0)?12:(val_==1)?1:(val_==2)?1:(val_==3)?0:(val_==4)?1:0;
endcase
endfunction
function integer bram_decompose_table;
input integer index;//Mode type
input integer val_; //Port A index, Port B Index, Number of Items in Loop, Port A Start, Port B Start, reserved
case (index)
0: bram_decompose_table=(val_==0)? 0:(val_==1)? 0:(val_==2)? 1:(val_==3)? 0:(val_==4)? 0:0;
endcase
endfunction
function integer bram_mapping_table;
input integer index;//Mode type
input integer val_;// Y, X, DataA [MSB], DataA [LSB], DataA Repeat, Read MuxA, Wen0 SelA, Wen1 SelA, Byteen A, DataB [MSB], DataB [LSB], DataB Repeat, Read MuxB, Wen0 SelB, Wen1 SelB, Byteen B, Addr Width A Data Width A Addr Width B Data Width B
case (index)
0: bram_mapping_table=(val_== 0)? 0:(val_== 1)? 0:(val_== 2)? 7:(val_== 3)? 0:(val_== 4)? 0:(val_== 5)? 0:(val_== 6)? 0:(val_== 7)? 0:(val_== 8)? 0:(val_== 9)? 7:(val_==10)? 0:(val_==11)? 0:(val_==12)? 0:(val_==13)? 0:(val_==14)? 0:(val_==15)? 0:(val_==16)? 8:(val_==17)? 20:(val_==18)? 8:(val_==19)? 20:0;
endcase
endfunction
function integer rMux_mapping_table_A;
input integer index;//Mode type
input integer val_;// PortA Addr MSB, PortA Addr LSB, DataA[MSB], DataA[LSB], MuxSelA[MSB], MuxSelA[LSB], Bypass,
rMux_mapping_table_A = 0;
endfunction
function integer rMux_mapping_table_B;
input integer index;//Mode type
input integer val_;// PortB Addr MSB, PortB Addr LSB, DataB[MSB], DataB[LSB], MuxSelB[MSB], MuxSelB[LSB], Bypass,
rMux_mapping_table_B = 0;
endfunction
function integer wen_sel_mapping_table_A;
input integer index;//Mode type
input integer val_;// PortA Addr MSB, PortA Addr LSB, WenSelA[MSB], WenSelA[LSB], Bypass,
wen_sel_mapping_table_A = 0;
endfunction
function integer wen_sel_mapping_table_B;
input integer index;//Mode type
input integer val_;// PortB Addr MSB, PortB Addr LSB, WenSelB[MSB], WenSelB[LSB], Bypass,
wen_sel_mapping_table_B = 0;
endfunction
function integer data_mapping_table_A;
input integer index;//
data_mapping_table_A = 0;
endfunction
function integer data_mapping_table_B;
input integer index;//
data_mapping_table_B = 0;
endfunction
function integer address_mapping_table_A;
input integer index;//
address_mapping_table_A = 0;
endfunction
function integer address_mapping_table_B;
input integer index;//
address_mapping_table_B = 0;
endfunction

49
hw/efinix_fpga/ip/bram/bram_ini.vh Normal file
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@@ -0,0 +1,49 @@
function [255:0] bram_ini_table;
input integer index;//Mode type
input integer val_; //Port A index, Port B Index, Number of Items in Loop, Port A Start, Port B Start, reserved
case (index)
0: bram_ini_table=
(val_== 0)?256'h0000000000000000000000000000000000000000000000000000010004c000ea:
(val_== 1)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_== 2)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_== 3)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_== 4)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_== 5)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_== 6)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_== 7)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_== 8)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_== 9)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==10)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==11)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==12)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==13)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==14)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==15)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==16)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==17)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==18)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==19)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==20)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==21)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==22)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==23)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==24)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==25)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==26)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==27)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==28)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==29)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==30)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==31)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==32)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==33)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==34)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==35)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==36)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==37)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==38)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==39)?256'h0000000000000000000000000000000000000000000000000000000000000000:
0;
endcase
endfunction

281
hw/efinix_fpga/ip/bram/bram_primitive.v Normal file
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@@ -0,0 +1,281 @@
////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
// / / \
// / / .. / bram_primitive.v
// / / .' /
// __/ /.' / Description:
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 0.0 Initial rev
//
// *******************************
module bram_primitive #(
parameter FAMILY = 0, //0:Trion, 1:Titanium
//Trion and Titanium parameters
parameter WRITE_WIDTH = 16, // write width
parameter WCLK_POLARITY = 1'b1, //wclk polarity, 0:falling edge, 1:rising edge
parameter WCLKE_POLARITY = 1'b1, //wclke polarity, 0:active low, 1:active high
parameter WE_POLARITY = 1'b1, //we polarity, 0:active low, 1:active high
parameter WRITE_MODE = "READ_FIRST",//write mode, "READ_FIRST" :Old memory content is read. (default)
// "WRITE_FIRST" :Write data is passed to the read port.
// "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict.
parameter READ_WIDTH = 16, // read width
parameter RCLK_POLARITY = 1'b1, // rclk polarity, 0:falling edge, 1:rising edge
parameter RE_POLARITY = 1'b1, // re polarity, 0:active low , 1:active high
parameter OUTPUT_REG = 1'b0, // Output register enable, 1:add pipe-line read register
//Titanium extra paramters
parameter RST_POLARITY = 1'b1, // rst polarity
parameter RESET_RAM = "ASYNC", // reset mode on ram, "NONE": RST signals does not affect the RAM output.
// "ASYNC": RAM output resets asynchronously to RCLK.
// "SYNC": RAM output resets synchronously to RCLK.
parameter RESET_OUTREG = "ASYNC", // reset mode on output register
// "NONE": RST signals does not affect the RAM output register
// "ASYNC": RAM output register resets asynchronously to RCLK.
parameter WADDREN_POLARITY = 1'b1, // waddren polarity
parameter RADDREN_POLARITY = 1'b1, // raddren polarity
//Titanium Option for byte enable in WEN width = 2 when it is Mode 512x16 or 512x20
parameter WEN_WIDTH = 1,
parameter ini_index = 0
)
(
//Trion and Titanium ports
WCLK, // Write clock input
WCLKE, // Write clock-enable input
WE, // Write-enable input
WADDR, // Write address input
WDATA, // Write data input
RCLK, // Read clock input
RE, // Read-enable input
RADDR, // Read address input
RDATA, // Read data output
//Titanium extra ports
RST, // reset
WADDREN, // write address enable
RADDREN // read address enable
);
function integer address_map;
input integer index;//Input data width parameter
input integer type; //Mapped data width, Mapped Address Width for Ram 5K(Trion), Mapped Address Width for Ram 10K(Titanium), WEN width for Ram 5K(Trion), WEN width for Ram 10K(Titanium)
case (index)
0 : address_map= (type==0)? 1 :(type==1)? 12 :(type==2)? 13 :1;
1 : address_map= (type==0)? 1 :(type==1)? 12 :(type==2)? 13 :1;
2 : address_map= (type==0)? 2 :(type==1)? 11 :(type==2)? 12 :1;
3 : address_map= (type==0)? 4 :(type==1)? 10 :(type==2)? 11 :1;
4 : address_map= (type==0)? 4 :(type==1)? 10 :(type==2)? 11 :1;
5 : address_map= (type==0)? 5 :(type==1)? 10 :(type==2)? 11 :1;
6 : address_map= (type==0)? 8 :(type==1)? 9 :(type==2)? 10 :1;
7 : address_map= (type==0)? 8 :(type==1)? 9 :(type==2)? 10 :1;
8 : address_map= (type==0)? 8 :(type==1)? 9 :(type==2)? 10 :1;
9 : address_map= (type==0)? 10 :(type==1)? 9 :(type==2)? 10 :1;
10 : address_map= (type==0)? 10 :(type==1)? 9 :(type==2)? 10 :1;
11 : address_map= (type==0)? 16 :(type==1)? 8 :(type==2)? 9 :1;
12 : address_map= (type==0)? 16 :(type==1)? 8 :(type==2)? 9 :1;
13 : address_map= (type==0)? 16 :(type==1)? 8 :(type==2)? 9 :1;
14 : address_map= (type==0)? 16 :(type==1)? 8 :(type==2)? 9 :1;
15 : address_map= (type==0)? 16 :(type==1)? 8 :(type==2)? 9 :1;
16 : address_map= (type==0)? 16 :(type==1)? 8 :(type==2)? 9 :1;
17 : address_map= (type==0)? 20 :(type==1)? 8 :(type==2)? 9 :1;
18 : address_map= (type==0)? 20 :(type==1)? 8 :(type==2)? 9 :1;
19 : address_map= (type==0)? 20 :(type==1)? 8 :(type==2)? 9 :1;
20 : address_map= (type==0)? 20 :(type==1)? 8 :(type==2)? 9 :1;
endcase
endfunction
localparam WRITE_DATA_WIDTH = address_map(WRITE_WIDTH,0);
localparam WRITE_ADDRESS_WIDTH = address_map(WRITE_WIDTH,(FAMILY==0)?1:2);
localparam READ_DATA_WIDTH = address_map(READ_WIDTH,0);
localparam READ_ADDRESS_WIDTH = address_map(READ_WIDTH,(FAMILY==0)?1:2);
//Trion and Titanium ports
input WCLK; // Write clock input
input WCLKE; // Write clock-enable input
input [WEN_WIDTH-1:0] WE; // Write-enable input
input [WRITE_ADDRESS_WIDTH-1:0] WADDR; // Write address input
input [WRITE_DATA_WIDTH-1:0] WDATA; // Write data input
input RCLK; // Read clock input
input RE; // Read-enable input
input [READ_ADDRESS_WIDTH-1:0] RADDR; // Read address input
output[READ_DATA_WIDTH-1:0]RDATA; // Read data output
//Titanium extra ports
input RST; // reset
input WADDREN; // write address enable
input RADDREN; // read address enable
`include "bram_ini.vh"
parameter filePath = "bram_ini.vh";
integer fd;
generate
initial begin
fd = $fopen(filePath, "r");
$fclose(fd);
end
if (FAMILY==0)
begin
EFX_RAM_5K # (
.WRITE_WIDTH (WRITE_WIDTH),
.WCLK_POLARITY (WCLK_POLARITY),
.WCLKE_POLARITY (WCLKE_POLARITY),
.WE_POLARITY (WE_POLARITY),
.WRITE_MODE (WRITE_MODE),
.READ_WIDTH (READ_WIDTH),
.RCLK_POLARITY (RCLK_POLARITY),
.RE_POLARITY (RE_POLARITY),
.OUTPUT_REG (OUTPUT_REG),
.INIT_0 (bram_ini_table(ini_index,16'h0 )),
.INIT_1 (bram_ini_table(ini_index,16'h1 )),
.INIT_2 (bram_ini_table(ini_index,16'h2 )),
.INIT_3 (bram_ini_table(ini_index,16'h3 )),
.INIT_4 (bram_ini_table(ini_index,16'h4 )),
.INIT_5 (bram_ini_table(ini_index,16'h5 )),
.INIT_6 (bram_ini_table(ini_index,16'h6 )),
.INIT_7 (bram_ini_table(ini_index,16'h7 )),
.INIT_8 (bram_ini_table(ini_index,16'h8 )),
.INIT_9 (bram_ini_table(ini_index,16'h9 )),
.INIT_A (bram_ini_table(ini_index,16'hA )),
.INIT_B (bram_ini_table(ini_index,16'hB )),
.INIT_C (bram_ini_table(ini_index,16'hC )),
.INIT_D (bram_ini_table(ini_index,16'hD )),
.INIT_E (bram_ini_table(ini_index,16'hE )),
.INIT_F (bram_ini_table(ini_index,16'hF )),
.INIT_10 (bram_ini_table(ini_index,16'h10)),
.INIT_11 (bram_ini_table(ini_index,16'h11)),
.INIT_12 (bram_ini_table(ini_index,16'h12)),
.INIT_13 (bram_ini_table(ini_index,16'h13))
)
ram5k (
.WCLK(WCLK), // Write clock input
.WE(WE[0]), // Write-enable input
.WCLKE(WCLKE), // Write clock-enable input
.WADDR(WADDR), // Write address input
.WDATA(WDATA), // Write data input
.RCLK(RCLK), // Read clock input
.RE(RE), // Read-enable input
.RADDR(RADDR), // Read address input
.RDATA(RDATA) // Read data output
);
end
else
begin
wire [1:0]w_wen_ram10;
assign w_wen_ram10[0] = WE[0];
if (WEN_WIDTH>1)
assign w_wen_ram10[1] = WE[1];
else if (WRITE_DATA_WIDTH >= 16 )
assign w_wen_ram10[1] = WE[0];
else
assign w_wen_ram10[1] = 1'b0;
EFX_RAM10 # (
.WRITE_WIDTH (WRITE_WIDTH),
.WCLK_POLARITY (WCLK_POLARITY),
.WCLKE_POLARITY (WCLKE_POLARITY),
.WE_POLARITY (WE_POLARITY),
.WRITE_MODE (WRITE_MODE),
.READ_WIDTH (READ_WIDTH),
.RCLK_POLARITY (RCLK_POLARITY),
.RE_POLARITY (RE_POLARITY),
.OUTPUT_REG (OUTPUT_REG),
//Titanium extra paramters
.RST_POLARITY (RST_POLARITY), // rst polarity
.RESET_RAM (RESET_RAM), // reset mode on ram
.RESET_OUTREG (RESET_OUTREG), // reset mode on output register
.WADDREN_POLARITY (WADDREN_POLARITY), // waddren polarity
.RADDREN_POLARITY (RADDREN_POLARITY), // raddren polarity
.INIT_0 (bram_ini_table(ini_index, 16'h0 )),
.INIT_1 (bram_ini_table(ini_index, 16'h1 )),
.INIT_2 (bram_ini_table(ini_index, 16'h2 )),
.INIT_3 (bram_ini_table(ini_index, 16'h3 )),
.INIT_4 (bram_ini_table(ini_index, 16'h4 )),
.INIT_5 (bram_ini_table(ini_index, 16'h5 )),
.INIT_6 (bram_ini_table(ini_index, 16'h6 )),
.INIT_7 (bram_ini_table(ini_index, 16'h7 )),
.INIT_8 (bram_ini_table(ini_index, 16'h8 )),
.INIT_9 (bram_ini_table(ini_index, 16'h9 )),
.INIT_A (bram_ini_table(ini_index, 16'hA )),
.INIT_B (bram_ini_table(ini_index, 16'hB )),
.INIT_C (bram_ini_table(ini_index, 16'hC )),
.INIT_D (bram_ini_table(ini_index, 16'hD )),
.INIT_E (bram_ini_table(ini_index, 16'hE )),
.INIT_F (bram_ini_table(ini_index, 16'hF )),
.INIT_10 (bram_ini_table(ini_index, 16'h10)),
.INIT_11 (bram_ini_table(ini_index, 16'h11)),
.INIT_12 (bram_ini_table(ini_index, 16'h12)),
.INIT_13 (bram_ini_table(ini_index, 16'h13)),
.INIT_14 (bram_ini_table(ini_index, 16'h14)),
.INIT_15 (bram_ini_table(ini_index, 16'h15)),
.INIT_16 (bram_ini_table(ini_index, 16'h16)),
.INIT_17 (bram_ini_table(ini_index, 16'h17)),
.INIT_18 (bram_ini_table(ini_index, 16'h18)),
.INIT_19 (bram_ini_table(ini_index, 16'h19)),
.INIT_1A (bram_ini_table(ini_index, 16'h1A)),
.INIT_1B (bram_ini_table(ini_index, 16'h1B)),
.INIT_1C (bram_ini_table(ini_index, 16'h1C)),
.INIT_1D (bram_ini_table(ini_index, 16'h1D)),
.INIT_1E (bram_ini_table(ini_index, 16'h1E)),
.INIT_1F (bram_ini_table(ini_index, 16'h1F)),
.INIT_20 (bram_ini_table(ini_index, 16'h20)),
.INIT_21 (bram_ini_table(ini_index, 16'h21)),
.INIT_22 (bram_ini_table(ini_index, 16'h22)),
.INIT_23 (bram_ini_table(ini_index, 16'h23)),
.INIT_24 (bram_ini_table(ini_index, 16'h24)),
.INIT_25 (bram_ini_table(ini_index, 16'h25)),
.INIT_26 (bram_ini_table(ini_index, 16'h26)),
.INIT_27 (bram_ini_table(ini_index, 16'h27))
)
ram10k(
.WCLK(WCLK), // Write clock input
.WE(w_wen_ram10), // Write-enable input
.WCLKE(WCLKE), // Write clock-enable input
.WADDR(WADDR), // Write address input
.WDATA(WDATA), // Write data input
.RCLK(RCLK), // Read clock input
.RE(RE), // Read-enable input
.RADDR(RADDR), // Read address input
.RDATA(RDATA), // Read data output
//Titanium extra ports
.RST (RST), // reset
.WADDREN (WADDREN), // write address enable
.RADDREN (RADDREN) // read address enable
);
end
endgenerate
endmodule

635
hw/efinix_fpga/ip/bram/bram_wrapper_mwm.v Normal file
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////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
// / / \
// / / .. / tb_top.v
// / / .' /
// __/ /.' / Description:
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 0.0 Initial rev
//
// *******************************
module bram_wrapper_mwm #(
//parameter FAMILY = 0, //0:Trion, 1:Titanium
//Trion and Titanium parameters
parameter WCLK_POLARITY = 1'b1, //wclk polarity, 0:falling edge, 1:rising edge
parameter WCLKE_POLARITY = 1'b1, //wclke polarity, 0:active low, 1:active high
parameter WE_POLARITY = 1'b1, //we polarity, 0:active low, 1:active high
parameter WRITE_MODE = "READ_FIRST",//write mode, "READ_FIRST" :Old memory content is read. (default)
// "WRITE_FIRST" :Write data is passed to the read port.
// "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict.
parameter RCLK_POLARITY = 1'b1, // rclk polarity, 0:falling edge, 1:rising edge
parameter RE_POLARITY = 1'b1, // re polarity, 0:active low , 1:active high
parameter OUTPUT_REG = 1'b0, // Output register enable, 1:add pipe-line read register
parameter BYTEEN_POLARITY = 1'b1, // byteen polarity 0:active low, 1:active high
//Titanium extra paramters
parameter RST_POLARITY = 1'b1, // rst polarity
parameter RESET_RAM = "ASYNC", // reset mode on ram, "NONE": RST signals does not affect the RAM output.
// "ASYNC": RAM output resets asynchronously to RCLK.
// "SYNC": RAM output resets synchronously to RCLK.
parameter RESET_OUTREG = "ASYNC", // reset mode on output register
// "NONE": RST signals does not affect the RAM output register
// "ASYNC": RAM output register resets asynchronously to RCLK.
parameter WADDREN_POLARITY = 1'b1, // waddren polarity
parameter RADDREN_POLARITY = 1'b1 // raddren polarity
)
(
//Trion and Titanium ports
wclk, // Write clock input
wclke, // Write clock-enable input
byteen, // Byteen input
we, // Write-enable input
waddr, // Write address input
wdata, // Write data input
rclk, // Read clock input
re, // Read-enable input
raddr, // Read address input
rdata, // Read data output
//Titanium extra ports
reset, // reset
waddren, // write address enable
raddren // read address enable
);
`include "bram_decompose.vh"
//`include "bram_feature.vh"
input wclk;
input wclke;
input we;
input [BYTEEN_WIDTH-1:0] byteen;
input [ADDR_WIDTH_A-1:0 ] waddr;
input [DATA_WIDTH_A-1:0 ] wdata;
input rclk;
input re;
input [ADDR_WIDTH_B-1:0 ] raddr;
output [DATA_WIDTH_B-1:0 ]rdata;
input reset;
input waddren;
input raddren;
wire [ADDR_WIDTH_A-1:0 ] w_waddr_map;
wire [DATA_WIDTH_A-1:0 ] w_wdata_map;
wire [ADDR_WIDTH_B-1:0 ] w_raddr_map;
wire [DATA_WIDTH_B-1:0 ] w_rdata_map;
function integer get_current_row_index;
input integer row;//Mode type
integer x;
begin
get_current_row_index = 0;
for (x=0; x<bram_mapping_size; x=x+1)
begin
if (bram_mapping_table(x,0) < row)
get_current_row_index = get_current_row_index +1;
end
end
endfunction
function integer get_current_column_index;
input integer column;//Mode type
integer x;
begin
get_current_column_index = 0;
for (x=0; x<bram_mapping_size; x=x+1)
begin
if (bram_mapping_table(x,1) < column)
get_current_column_index = get_current_column_index +1;
end
end
endfunction
function integer get_max_mux_row_A;
input integer temp;//Mode type
integer x;
begin
get_max_mux_row_A = 0;
for (x=0; x<bram_mapping_size; x=x+1)
begin
if ( get_max_mux_row_A < bram_mapping_table(x,5) )
get_max_mux_row_A = bram_mapping_table(x,5);
end
end
endfunction
function integer get_max_wen_decode_A;
input integer temp;//Mode type
integer x;
begin
get_max_wen_decode_A = 0;
for (x=0; x<bram_mapping_size; x=x+1)
begin
if ( get_max_wen_decode_A < bram_mapping_table(x,6) )
get_max_wen_decode_A = bram_mapping_table(x,6);
end
end
endfunction
function integer get_max_mux_row_B;
input integer temp;//Mode type
integer x;
begin
get_max_mux_row_B = 0;
for (x=0; x<bram_mapping_size; x=x+1)
begin
if ( get_max_mux_row_B < bram_mapping_table(x,12) )
get_max_mux_row_B = bram_mapping_table(x,12);
end
end
endfunction
function integer get_max_wen_decode_B;
input integer temp;//Mode type
integer x;
begin
get_max_wen_decode_B = 0;
for (x=0; x<bram_mapping_size; x=x+1)
begin
if ( get_max_wen_decode_B < bram_mapping_table(x,13) )
get_max_wen_decode_B = bram_mapping_table(x,13);
end
end
endfunction
// localparam column_size = (bram_table_loop_mode==1)?bram_table_size:1;
// wire [DATA_WIDTH_B-1:0] w_rdata [bram_table_size-1:0 ];
// assign rdata = w_rdata[wdata];
genvar gen_x;
genvar gen_y;
genvar gen_z;
generate
wire [DATA_WIDTH_B-1:0 ] rMux [get_max_mux_row_B(0):0];
if (rMux_mapping_B_size == 0)
begin
assign w_rdata_map = rMux[0];
end
else
begin
for (gen_y=0; gen_y<rMux_mapping_B_size; gen_y =gen_y +1)
begin:rDataMux
localparam ADDR_START = rMux_mapping_table_B(gen_y,1);
localparam ADDR_END = rMux_mapping_table_B(gen_y,0);
localparam DATA_START = rMux_mapping_table_B(gen_y,3);
localparam DATA_END = rMux_mapping_table_B(gen_y,2);
localparam BYPRASSED = rMux_mapping_table_A(gen_y,6);
if( BYPRASSED == 0 )
begin
wire [ADDR_END:ADDR_START] rdSel;
reg [ADDR_END:ADDR_START] r_rdSel_1P;
assign rdSel = w_raddr_map[ADDR_END:ADDR_START];
always @ (posedge rclk)
begin
r_rdSel_1P <= rdSel;
end
if (OUTPUT_REG == 0)
begin
assign w_rdata_map[DATA_END:DATA_START] = rMux[r_rdSel_1P][DATA_END:DATA_START];
end
else
begin
reg [ADDR_END:ADDR_START] r_rdSel_2P;
always @ (posedge rclk)
begin
r_rdSel_2P <= r_rdSel_1P;
end
assign w_rdata_map[DATA_END:DATA_START] = rMux[r_rdSel_2P][DATA_END:DATA_START];
end
end
else
begin
assign w_rdata_map[DATA_END:DATA_START] = rMux[0][DATA_END:DATA_START];
end
end
end
wire [get_max_wen_decode_A(0):0] wen_decode ;
if (wen_sel_mapping_A_size!=0)
begin
for (gen_y=0; gen_y<wen_sel_mapping_A_size; gen_y =gen_y +1)
begin:wDataEn
localparam ADDR_START = wen_sel_mapping_table_A(gen_y,1);
localparam ADDR_END = wen_sel_mapping_table_A(gen_y,0);
localparam SEL_START = wen_sel_mapping_table_A(gen_y,3);
localparam SEL_END = wen_sel_mapping_table_A(gen_y,2);
localparam BYPRASSED = wen_sel_mapping_table_A(gen_y,4);
if( BYPRASSED == 0 )
begin
wire [ADDR_END:ADDR_START] wrSel;
assign wrSel = w_waddr_map[ADDR_END:ADDR_START];
for (gen_x=SEL_START; gen_x<(SEL_END+1); gen_x = gen_x +1)
begin
assign wen_decode[gen_x] = (wrSel==(gen_x-SEL_START))?1'b1:1'b0;
end
end
else
begin
for (gen_x=SEL_START; gen_x<(SEL_END+1); gen_x = gen_x +1)
begin
assign wen_decode[gen_x] = 1'b1;
end
end
end
end
else
begin
assign wen_decode = {(get_max_wen_decode_A(0)+1){1'b1}};
end
//For Mixed Width Mode
if (data_mapping_table_A_size!=0)
begin
for (gen_y=0; gen_y<data_mapping_table_A_size; gen_y = gen_y +1)
begin
assign w_wdata_map[data_mapping_table_A(gen_y)] = wdata[gen_y] ;
end
end
else
begin
assign w_wdata_map = wdata;
end
if (address_mapping_table_A_size!=0)
begin
for (gen_y=0; gen_y<address_mapping_table_A_size; gen_y = gen_y +1)
begin
assign w_waddr_map[address_mapping_table_A(gen_y)] = waddr[gen_y] ;
end
end
else
begin
assign w_waddr_map = waddr;
end
if (data_mapping_table_B_size!=0)
begin
for (gen_y=0; gen_y<data_mapping_table_B_size; gen_y = gen_y +1)
begin
assign rdata[gen_y] = w_rdata_map[data_mapping_table_B(gen_y)] ;
end
end
else
begin
assign rdata = w_rdata_map;
end
if (address_mapping_table_B_size!=0)
begin
for (gen_y=0; gen_y<address_mapping_table_B_size; gen_y = gen_y +1)
begin
assign w_raddr_map[address_mapping_table_B(gen_y)] = raddr[gen_y] ;
end
end
else
begin
assign w_raddr_map = raddr;
end
if (bram_table_loop_mode == 0 )
begin:scan_column
for (gen_x=0; gen_x<bram_table_size; gen_x =gen_x +1)
begin:column
localparam bram_mode_a = bram_decompose_table(gen_x,0);
localparam bram_mode_b = bram_decompose_table(gen_x,1);
localparam row_count = bram_decompose_table(gen_x,2);
localparam WADDR_WIDTH_ROW = bram_feature_table(bram_mode_a,0);
localparam WDATA_WIDTH_ROW = bram_feature_table(bram_mode_a,1);
localparam WEN_WIDTH_ROW = bram_feature_table(bram_mode_a,2);
localparam RADDR_WIDTH_ROW = bram_feature_table(bram_mode_b,0);
localparam RDATA_WIDTH_ROW = bram_feature_table(bram_mode_b,1);
localparam START_COLUMN_INDEX = get_current_column_index(gen_x);
for (gen_y=0; gen_y<row_count; gen_y =gen_y +1)
begin:row
localparam DATA_MAP_INDEX = START_COLUMN_INDEX+gen_y;
localparam WDATA_END = bram_mapping_table(DATA_MAP_INDEX,2);
localparam WDATA_START = bram_mapping_table(DATA_MAP_INDEX,3);
localparam WDATA_REPART = bram_mapping_table(DATA_MAP_INDEX,4);
localparam WRSEL_INDEX = bram_mapping_table(DATA_MAP_INDEX,6);
localparam BYTEEN_INDEX = bram_mapping_table(DATA_MAP_INDEX,8);
localparam RDATA_END = bram_mapping_table(DATA_MAP_INDEX,9);
localparam RDATA_START = bram_mapping_table(DATA_MAP_INDEX,10);
localparam RDATA_REPART = bram_mapping_table(DATA_MAP_INDEX,11);
localparam RMUX_INDEX = bram_mapping_table(DATA_MAP_INDEX,12);
wire [WADDR_WIDTH_ROW-1:0] w_waddr;
wire [WDATA_WIDTH_ROW-1:0] w_wdata;
wire [WEN_WIDTH_ROW-1:0] w_we;
wire [RADDR_WIDTH_ROW-1:0] w_raddr;
wire [RDATA_WIDTH_ROW-1:0] w_rdata;
assign w_waddr[WADDR_WIDTH_ROW-1:0] = w_waddr_map[WADDR_WIDTH_ROW-1:0];
assign w_raddr[RADDR_WIDTH_ROW-1:0] = w_raddr_map[RADDR_WIDTH_ROW-1:0];
if (WDATA_REPART == 0)
begin
assign w_wdata[WDATA_WIDTH_ROW-1:0] = w_wdata_map[WDATA_END:WDATA_START];
end
else
begin
//for Mixed Width Mode
for (gen_z=0; gen_z<WDATA_REPART; gen_z = gen_z+1)
begin
localparam MIXED_WDATA_START = WDATA_START + gen_z*row_count*(RDATA_END - RDATA_START+1); //RDATA_WIDTH_ROW;
localparam MIXED_WDATA_END = WDATA_END + gen_z*row_count*(RDATA_END - RDATA_START+1); //RDATA_WIDTH_ROW;
localparam MAPPED_WDATA_START = RDATA_WIDTH_ROW* gen_z;
localparam MAPPED_WDATA_END = RDATA_WIDTH_ROW*(gen_z+1) -1;
assign w_wdata[MAPPED_WDATA_END: MAPPED_WDATA_START] = w_wdata_map[MIXED_WDATA_END:MIXED_WDATA_START];
end
end
if (RDATA_REPART == 0)
begin
assign rMux[RMUX_INDEX][RDATA_END:RDATA_START] = w_rdata[RDATA_WIDTH_ROW-1:0];
end
else
begin
//for Mixed Width Mode
for (gen_z=0; gen_z<RDATA_REPART; gen_z = gen_z+1)
begin
localparam MIXED_RDATA_START = RDATA_START + gen_z*row_count*(WDATA_END - WDATA_START+1); //WDATA_WIDTH_ROW;
localparam MIXED_RDATA_END = RDATA_END + gen_z*row_count*(WDATA_END - WDATA_START+1); //WDATA_WIDTH_ROW;
localparam MAPPED_RDATA_START = RDATA_WIDTH_ROW* gen_z;
localparam MAPPED_RDATA_END = RDATA_WIDTH_ROW*(gen_z+1) -1;
assign rMux[RMUX_INDEX][MIXED_RDATA_END:MIXED_RDATA_START] = w_rdata[MAPPED_RDATA_END:MAPPED_RDATA_START];
end
end
assign w_we[0] = ((we == WE_POLARITY) & wen_decode[WRSEL_INDEX] & (byteen[BYTEEN_INDEX] == BYTEEN_POLARITY) )? WE_POLARITY: !WE_POLARITY;
if ( WEN_WIDTH_ROW >1)
begin
assign w_we[1] = ((we == WE_POLARITY) & wen_decode[WRSEL_INDEX] & (byteen[BYTEEN_INDEX] == BYTEEN_POLARITY) ) ? WE_POLARITY: !WE_POLARITY;
end
bram_primitive #(
.FAMILY(FAMILY), //0:Trion, 1:Titanium
//Trion and Titanium parameters
.WRITE_WIDTH(WDATA_WIDTH_ROW),
.WCLK_POLARITY(WCLK_POLARITY),
.WCLKE_POLARITY(WCLKE_POLARITY),
.WE_POLARITY(WE_POLARITY),
.WRITE_MODE(WRITE_MODE),
.READ_WIDTH(RDATA_WIDTH_ROW),
.RCLK_POLARITY(RCLK_POLARITY),
.RE_POLARITY(RE_POLARITY),
.OUTPUT_REG(OUTPUT_REG),
//Titanium extra paramters
.RST_POLARITY(RST_POLARITY),
.RESET_RAM(RESET_RAM),
.RESET_OUTREG(RESET_OUTREG),
.WADDREN_POLARITY(WADDREN_POLARITY),
.RADDREN_POLARITY(RADDREN_POLARITY),
.WEN_WIDTH(WEN_WIDTH_ROW),
.ini_index(DATA_MAP_INDEX)
) bram (
//Trion and Titanium ports
.WCLK(wclk), // Write clock input
.WCLKE(wclke), // Write clock-enable input
.WE(w_we), // Write-enable input
.WADDR(w_waddr), // Write address input
.WDATA(w_wdata), // Write data input
.RCLK(rclk), // Read clock input
.RE(re), // Read-enable input
.RADDR(w_raddr), // Read address input
.RDATA(w_rdata), // Read data output
//Titanium extra ports
.RST(reset), // reset
.WADDREN(waddren), // write address enable
.RADDREN(raddren) // read address enable
);
end
end
end
else if (bram_table_loop_mode == 1 )
begin:scan_row
for (gen_y=0; gen_y<bram_table_size; gen_y =gen_y +1)
begin:row
localparam bram_mode_a = bram_decompose_table(gen_y,0);
localparam bram_mode_b = bram_decompose_table(gen_y,1);
localparam column_count = bram_decompose_table(gen_y,2);
localparam WADDR_WIDTH_ROW = bram_feature_table(bram_mode_a,0);
localparam WDATA_WIDTH_ROW = bram_feature_table(bram_mode_a,1);
localparam WEN_WIDTH_ROW = bram_feature_table(bram_mode_a,2);
localparam RADDR_WIDTH_ROW = bram_feature_table(bram_mode_b,0);
localparam RDATA_WIDTH_ROW = bram_feature_table(bram_mode_b,1);
localparam START_ROW_INDEX = get_current_row_index(gen_y);
for (gen_x=0; gen_x<column_count; gen_x =gen_x +1)
begin:column
localparam DATA_MAP_INDEX = START_ROW_INDEX+gen_x;
localparam WDATA_END = bram_mapping_table(DATA_MAP_INDEX,2);
localparam WDATA_START = bram_mapping_table(DATA_MAP_INDEX,3);
localparam WDATA_REPART = bram_mapping_table(DATA_MAP_INDEX,4);
localparam WRSEL_INDEX = bram_mapping_table(DATA_MAP_INDEX,6);
localparam BYTEEN_INDEX = bram_mapping_table(DATA_MAP_INDEX,8);
localparam RDATA_END = bram_mapping_table(DATA_MAP_INDEX,9);
localparam RDATA_START = bram_mapping_table(DATA_MAP_INDEX,10);
localparam RDATA_REPART = bram_mapping_table(DATA_MAP_INDEX,11);
localparam RMUX_INDEX = bram_mapping_table(DATA_MAP_INDEX,12);
wire [WADDR_WIDTH_ROW-1:0] w_waddr;
wire [WDATA_WIDTH_ROW-1:0] w_wdata;
wire [WEN_WIDTH_ROW-1:0] w_we;
wire [RADDR_WIDTH_ROW-1:0] w_raddr;
wire [RDATA_WIDTH_ROW-1:0] w_rdata;
//assign w_waddr[WADDR_WIDTH_ROW-1:0] = w_waddr_map[WADDR_WIDTH_ROW-1:0];
//assign w_raddr[RADDR_WIDTH_ROW-1:0] = w_raddr_map[RADDR_WIDTH_ROW-1:0];
for(gen_z=0;gen_z<WADDR_WIDTH_ROW; gen_z=gen_z+1)
begin
if(gen_z< ADDR_WIDTH_A)
assign w_waddr[gen_z] = w_waddr_map[gen_z];
else
assign w_waddr[gen_z] = 1'b0;
end
for(gen_z=0;gen_z<RADDR_WIDTH_ROW; gen_z=gen_z+1)
begin
if(gen_z< ADDR_WIDTH_B)
assign w_raddr[gen_z] = w_raddr_map[gen_z];
else
assign w_raddr[gen_z] = 1'b0;
end
if (WDATA_REPART == 0)
begin
assign w_wdata[WDATA_WIDTH_ROW-1:0] = w_wdata_map[WDATA_END:WDATA_START];
end
else
begin
//for Mixed Width Mode
for (gen_z=0; gen_z<WDATA_REPART; gen_z = gen_z+1)
begin:MIXED_WIDTH_MAPPING
localparam MIXED_WDATA_START = WDATA_START + gen_z*column_count*(RDATA_END - RDATA_START+1); // RDATA_WIDTH_ROW;
localparam MIXED_WDATA_END = WDATA_END + gen_z*column_count*(RDATA_END - RDATA_START+1); //RDATA_WIDTH_ROW;
localparam MAPPED_WDATA_START = RDATA_WIDTH_ROW* gen_z;
localparam MAPPED_WDATA_END = RDATA_WIDTH_ROW*(gen_z+1) -1;
assign w_wdata[MAPPED_WDATA_END: MAPPED_WDATA_START] = w_wdata_map[MIXED_WDATA_END:MIXED_WDATA_START];
end
end
if (RDATA_REPART == 0)
begin
assign rMux[RMUX_INDEX][RDATA_END:RDATA_START] = w_rdata[RDATA_WIDTH_ROW-1:0];
end
else
begin
//for Mixed Width Mode
for (gen_z=0; gen_z<RDATA_REPART; gen_z = gen_z+1)
begin:MIXED_WIDTH_MAPPING
localparam MIXED_RDATA_START = RDATA_START + gen_z*column_count*(WDATA_END - WDATA_START+1); //WDATA_WIDTH_ROW;
localparam MIXED_RDATA_END = RDATA_END + gen_z*column_count*(WDATA_END - WDATA_START+1); //WDATA_WIDTH_ROW;
localparam MAPPED_RDATA_START = WDATA_WIDTH_ROW* gen_z;
localparam MAPPED_RDATA_END = WDATA_WIDTH_ROW*(gen_z+1) -1;
assign rMux[RMUX_INDEX][MIXED_RDATA_END:MIXED_RDATA_START] = w_rdata[MAPPED_RDATA_END:MAPPED_RDATA_START];
end
end
assign w_we[0] = ((we == WE_POLARITY) & wen_decode[WRSEL_INDEX] & (byteen[BYTEEN_INDEX] == BYTEEN_POLARITY)) ? WE_POLARITY: !WE_POLARITY;;
if ( WEN_WIDTH_ROW >1)
begin
assign w_we[1] = ((we == WE_POLARITY) & wen_decode[WRSEL_INDEX] & (byteen[BYTEEN_INDEX] == BYTEEN_POLARITY)) ? WE_POLARITY: !WE_POLARITY;;
end
bram_primitive #(
.FAMILY(FAMILY), //0:Trion, 1:Titanium
//Trion and Titanium parameters
.WRITE_WIDTH(WDATA_WIDTH_ROW),
.WCLK_POLARITY(WCLK_POLARITY),
.WCLKE_POLARITY(WCLKE_POLARITY),
.WE_POLARITY(WE_POLARITY),
.WRITE_MODE(WRITE_MODE),
.READ_WIDTH(RDATA_WIDTH_ROW),
.RCLK_POLARITY(RCLK_POLARITY),
.RE_POLARITY(RE_POLARITY),
.OUTPUT_REG(OUTPUT_REG),
//Titanium extra paramters
.RST_POLARITY(RST_POLARITY),
.RESET_RAM(RESET_RAM),
.RESET_OUTREG(RESET_OUTREG),
.WADDREN_POLARITY(WADDREN_POLARITY),
.RADDREN_POLARITY(RADDREN_POLARITY),
.WEN_WIDTH(WEN_WIDTH_ROW),
.ini_index(DATA_MAP_INDEX)
) bram (
//Trion and Titanium ports
.WCLK(wclk), // Write clock input
.WCLKE(wclke), // Write clock-enable input
.WE(w_we), // Write-enable input
.WADDR(w_waddr), // Write address input
.WDATA(w_wdata), // Write data input
.RCLK(rclk), // Read clock input
.RE(re), // Read-enable input
.RADDR(w_raddr), // Read address input
.RDATA(w_rdata), // Read data output
//Titanium extra ports
.RST(reset), // reset
.WADDREN(waddren), // write address enable
.RADDREN(raddren) // read address enable
);
end
end
end
endgenerate
endmodule

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hw/efinix_fpga/ip/bram/efx_mem_decompose_script.py Normal file
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hw/efinix_fpga/ip/bram/efx_mem_init_script.py Normal file
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"""
Copyright (C) 2022 Efinix Inc. All rights reserved.
No portion of this code may be reused, modified or
distributed in any way without the expressed written
consent of Efinix Inc.
Created on Dec 22, 2021
@author: Dragon Lai
"""
import sys
import os
import argparse
import math
import json
from enum import Enum
FAMILY = 0
in_addr_width_a = 0
in_data_width_a = 0
in_addr_width_b = 0
in_data_width_b = 0
actual_size_A = 0
actual_size_B = 0
byteen_width = 0
group_data_width = 0
group_columns = 0
bram_decompose_mode = 0
bram_feature_table = list()
group_columns = list()
bram_decompose_table = list()
bram_mapping_table = list()
rMux_mapping_table_A = list()
wen_sel_mapping_table_A = list()
rMux_mapping_table_B = list()
wen_sel_mapping_table_B = list()
data_mapping_table_A = list()
data_mapping_table_B = list()
address_mapping_table_A = list()
address_mapping_table_B = list()
mem_table = list()
def remove_comment(InString):
result = False
outString = InString
#find comment sytnax '//'
Index_start = InString.find('//')
#find end of line \n after //
if (Index_start != -1 ):
Index_end = InString.find('\n',Index_start)
if (Index_end == -1):
Index_end = len(InString)
if (Index_start == 0 ):
outString = InString[Index_end:]
else:
outString = InString[:Index_start] + InString[Index_end:]
result = True
return result, outString
def remove_comments(InString):
result = True
TempString = InString
while(result):
result, OutString = remove_comment(TempString)
TempString = OutString
return OutString
def dump2memTable(InString,in_format, port, in_data_width, in_addr_width):
ProcesseData = remove_comments(InString)
#print( in_format, in_data_width, in_addr_width)
#print(ProcesseData)
lines = ProcesseData.split()
#print(lines)
bit_count = 1
if (in_format == 'hex'):
bit_count = 4
line_ptr = 0
for line in lines:
if (line_ptr+1) > (2**in_addr_width):
break
bit_ptr = 0
for bits in reversed(line):
if (bit_ptr+1) > in_data_width:
break
value = int(bits, 16)
for x in range(0,bit_count):
# print ( line_ptr, bit_ptr)
if (bit_ptr+1) > in_data_width:
break
mem_table[line_ptr][bit_ptr] = (value % 2)
value = int(value / 2)
bit_ptr = bit_ptr + 1
#print(mem_table[line_ptr])
line_ptr = line_ptr+1
#print(mem_table)
create_memory_init_file(port,in_data_width, in_addr_width )
def create_prmitive_map(data_width, addr_width, primitive_addr_width, primiive_data_width, map_data_msb, map_data_lsb, repeat, interval, row_index):
#print(data_width, addr_width, primitive_addr_width, primiive_data_width, map_data_msb, map_data_lsb, repeat, row_index)
#print(data_width, addr_width, primitive_addr_width, primiive_data_width, map_data_msb, map_data_lsb, repeat, interval, row_index)
primitive_mem = list()
#initial primitive memory profile
for y in range(0,(2**primitive_addr_width)):
row = list()
for x in range(0,primiive_data_width):
row.append(int(0))
primitive_mem.append(row)
primitive_y = int(0)
primitive_x = int(0)
addr_start = row_index * (2**primitive_addr_width)
addr_End = (row_index+1)* (2**primitive_addr_width) -1
#print(addr_start, addr_End, primiive_data_width, map_data_lsb,map_data_msb )
if(addr_End > (2**addr_width)-1):
addr_End = (2**addr_width)-1
for y in range(addr_start, addr_End+1 ):
init_row = mem_table[y]
primitive_x = int(0)
if repeat == 0:
for x in range(map_data_lsb, map_data_msb +1 ) :
if (primitive_x+1) > primiive_data_width:
break
primitive_mem[primitive_y][primitive_x] = init_row[x]
primitive_x = primitive_x+1
#if (map_data_lsb == 10 ):
# print (y, primitive_y,primitive_x, primitive_mem[primitive_y], init_row, map_data_lsb,( map_data_msb-map_data_lsb) +1 )
else:
for r_x in range(0,repeat):
temp_data_lsb = map_data_lsb + (interval * r_x)
temp_data_msb = map_data_msb + (interval * r_x)
for x in range(temp_data_lsb, temp_data_msb +1 ) :
if (primitive_x+1) > primiive_data_width:
break
primitive_mem[primitive_y][primitive_x] = init_row[x]
primitive_x = primitive_x+1
primitive_y = primitive_y+1
#print(primitive_mem)
converted_init_mem = list()
#initial primitive init profile
for y in range(0,40):
row =list()
for x in range(0,32):
row.append(int(0))
converted_init_mem.append(row)
#initial primitive memory profile
primitive_bit_ptr = int(0)
primitive_byte = int(0)
primitive_x_ptr = int(31)
primitive_y_ptr = int(0)
for y in range(0,(2**primitive_addr_width)):
for x in range(0,primiive_data_width):
primitive_byte = primitive_byte + primitive_mem[y][x] * (2** primitive_bit_ptr)
primitive_bit_ptr = primitive_bit_ptr + 1
if primitive_bit_ptr >= 8:
converted_init_mem[primitive_y_ptr][primitive_x_ptr] = primitive_byte
primitive_bit_ptr = 0
primitive_byte = 0
primitive_x_ptr = primitive_x_ptr-1
if primitive_x_ptr < 0:
primitive_x_ptr = 31
primitive_y_ptr = primitive_y_ptr +1
if primitive_y_ptr >= 40:
break
return converted_init_mem
def create_memory_init_file(port, data_width, addr_width ):
f = open("bram_ini.vh", "w")
line = '\n'
line += 'function [255:0] bram_ini_table;\n'
line += 'input integer index;//Mode type \n'
line += 'input integer val_; //Port A index, Port B Index, Number of Items in Loop, Port A Start, Port B Start, reserved \n'
line += 'case (index)\n'
f.write (line)
y = 0
for row in bram_mapping_table:
line = ""
x = 0
line += '%4s: bram_ini_table=\n' %(y)
index_primitive_row = row[0]
index_primitive_column = row[1]
DataA_MSB = row[2]
DataA_LSB = row[3]
DataA_REPEAT = row[4]
DataA_RdMux = row[5]
DataB_MSB = row[9]
DataB_LSB = row[10]
DataB_REPEAT = row[11]
DataB_RdMux = row[12]
primitive_addrW_A = row[16]
primitive_dataW_A = row[17]
primitive_addrW_B = row[18]
primitive_dataW_B = row[19]
maptable = list()
if port == 'a':
maptable = create_prmitive_map(data_width, addr_width, primitive_addrW_A, primitive_dataW_A, DataA_MSB, DataA_LSB, DataA_REPEAT, in_data_width_b, DataA_RdMux)
elif port == 'b':
maptable = create_prmitive_map(data_width, addr_width, primitive_addrW_B, primitive_dataW_B, DataB_MSB, DataB_LSB, DataB_REPEAT, in_data_width_a, DataB_RdMux)
stringline = ""
for Values in maptable:
stringline ="256'h"
for value in Values:
stringline += '%02x' % (value)
line += '(val_==%2s)?' % (x)
line += stringline
line += ":\n"
x = x + 1
line += '0;\n'
f.write (line)
#stringline ="256'h"
#for hexChar in range(0,32):
# #stringline += '%02x' % (y)
# stringline += '%02x' % (0)
#
#
#for x in range(0, 40):
# #line += '(val_==' + str(x) + ')?' + str(feature) + ':'
# line += '(val_==%2s)?' % (x)
#
# line += stringline
# #line += "256'h0000000000000000000000000000000000000000000000000000000000000000"
#
# line += ":\n"
# x = x + 1
#line += '0;\n'
#f.write (line)
y = y +1
line = ""
line += " endcase\n"
line += "endfunction \n"
f.write (line)
f.close()
if __name__ == "__main__":
parser = argparse.ArgumentParser(description='Memory Decompose to BRAM')
parser.add_argument("format", choices=['hex', 'bin'], help="Memory file format")
parser.add_argument("init_file", help="Input file name")
parser.add_argument("--port", choices=['a', 'b'], default='b', help="inital data width based on port A(Write) , or port B(Read)")
# run parser
args = parser.parse_args()
text_file = open(args.init_file, "r")
try:
with open('mem_config.txt', 'r') as f:
mem_config = json.loads(f.read())
FAMILY = mem_config[0]
in_addr_width_a = mem_config[1]
in_data_width_a = mem_config[2]
in_addr_width_b = mem_config[3]
in_data_width_b = mem_config[4]
actual_size_A = mem_config[5]
actual_size_B = mem_config[6]
byteen_width = mem_config[7]
group_data_width = mem_config[8]
group_columns = mem_config[9]
bram_decompose_mode = mem_config[10]
bram_feature_table = mem_config[11]
group_columns = mem_config[12]
bram_decompose_table = mem_config[13]
bram_mapping_table = mem_config[14]
rMux_mapping_table_A = mem_config[15]
wen_sel_mapping_table_A = mem_config[16]
rMux_mapping_table_B = mem_config[17]
wen_sel_mapping_table_B = mem_config[18]
data_mapping_table_A = mem_config[19]
data_mapping_table_B = mem_config[20]
address_mapping_table_A = mem_config[21]
address_mapping_table_B = mem_config[22]
data_width = 0
addr_width = 0
if args.port == 'a':
data_width = in_data_width_a
addr_width = in_addr_width_a
elif args.port == 'b':
data_width = in_data_width_b
addr_width = in_addr_width_b
for y in range(0,2 ** addr_width):
column = list()
for x in range(0,data_width):
column.append(0)
mem_table.append(column)
#read whole file to a string
InString = text_file.read()
result = "Data width = " + str(data_width) + " Address width = " + str(addr_width)
print (result)
print ("Status : Memory Initialization has completed")
dump2memTable(InString,args.format,args.port, data_width, addr_width)
#close file
text_file.close()
except OSError as e:
print(f"{type(e)}: {e}")

153
hw/efinix_fpga/ip/bram/efx_single_port_ram.v Normal file
View File

@@ -0,0 +1,153 @@
////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
// / / \
// / / .. / efx_single_port_ram.v
// / / .' /
// __/ /.' / Description:
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 0.0 Initial rev
//
// *******************************
module efx_single_port_ram #(
//Trion and Titanium parameters
parameter CLK_POLARITY = 1'b1, //clk polarity, 0:falling edge, 1:rising edge
parameter WCLKE_POLARITY = 1'b1, //wclke polarity, 0:active low, 1:active high
parameter WE_POLARITY = 1'b1, //we polarity, 0:active low, 1:active high
parameter WRITE_MODE = "READ_UNKNOWN",//write mode, "READ_FIRST" :Old memory content is read. (default)
// "WRITE_FIRST" :Write data is passed to the read port.
// "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict.
parameter RE_POLARITY = 1'b1, // re polarity, 0:active low , 1:active high
parameter OUTPUT_REG = 1'b0, // Output register enable, 1:add pipe-line read register
parameter BYTEEN_POLARITY = 1'b1, //byteen polarity, 0:active low, 1:active high
//Port Enable
parameter WCLKE_ENABLE = 1'b1, //1: Enable the port for waddren pin , 0: disable
parameter WE_ENABLE = 1'b1, //1: Enable the port for WE pin , 0: disable
parameter RE_ENABLE = 1'b1, //1: Enable the port for RE pin , 0: disable
parameter BYTEEN_ENABLE = 1'b1, //1: Enable the port for Byteen pins , 0: disable
//Titanium extra paramters
parameter RST_POLARITY = 1'b1, // rst polarity
parameter RESET_RAM = "ASYNC", // reset mode on ram, "NONE": RST signals does not affect the RAM output.
// "ASYNC": RAM output resets asynchronously to RCLK.
// "SYNC": RAM output resets synchronously to RCLK.
parameter RESET_OUTREG = "ASYNC", // reset mode on output register
// "NONE": RST signals does not affect the RAM output register
// "ASYNC": RAM output register resets asynchronously to RCLK.
parameter ADDREN_POLARITY = 1'b1, // addren polarity
//Port Enable
parameter RESET_ENABLE = 1'b1, //1: Enable the port for reset pin , 0: disable
parameter ADDREN_ENABLE = 1'b1 //1: Enable the port for addren pin , 0: disable
)
(
//Trion and Titanium ports
clk, // clock input for one clock mode
addr, // address input
wclke, // Write clock-enable input
byteen, // Byteen input
we, // Write-enable input
wdata, // Write data input
re, // Read-enable input
rdata, // Read data output
//Titanium extra ports
reset, // reset
addren, // address enable
);
`include "bram_decompose.vh"
//Trion and Titanium ports
input clk;
input [ADDR_WIDTH_A-1:0] addr;
input wclke;
input [BYTEEN_WIDTH-1:0] byteen;
input we;
input [DATA_WIDTH_A-1:0] wdata;
input re;
output [DATA_WIDTH_B-1:0] rdata;
//Titanium extra ports
input reset;
input addren;
wire w_wclk;
wire w_rclk;
wire w_wclke;
wire [BYTEEN_WIDTH-1:0] w_byteen;
wire w_we;
wire w_re;
wire w_reset;
wire w_addren;
assign w_wclke = (WCLKE_ENABLE==1) ? wclke : WCLKE_POLARITY;
assign w_byteen= (BYTEEN_ENABLE==1) ? byteen : {BYTEEN_WIDTH{BYTEEN_POLARITY}};
assign w_we = (WE_ENABLE==1) ? we : WE_POLARITY;
assign w_re = (RE_ENABLE==1) ? re : RE_POLARITY;
//Titanium extra ports
assign w_reset = (RESET_ENABLE==1) ? reset : (RST_POLARITY==1'b1) ? 1'b0: 1'b1;
assign w_addren = (ADDREN_ENABLE==1)? addren : ADDREN_POLARITY;
bram_wrapper_mwm #(
//.FAMILY(FAMILY),
//Trion and Titanium parameters
.WCLK_POLARITY(CLK_POLARITY),
.WCLKE_POLARITY(WCLKE_POLARITY),
.WE_POLARITY(WE_POLARITY),
.WRITE_MODE(WRITE_MODE),
.RCLK_POLARITY(CLK_POLARITY),
.RE_POLARITY(RE_POLARITY),
.OUTPUT_REG(OUTPUT_REG),
.BYTEEN_POLARITY(BYTEEN_POLARITY),
//Titanium extra paramters
.RST_POLARITY(RST_POLARITY),
.RESET_RAM(RESET_RAM),
.RESET_OUTREG(RESET_OUTREG),
.WADDREN_POLARITY(ADDREN_POLARITY),
.RADDREN_POLARITY(ADDREN_POLARITY)
) brams (
.wclk(clk),
.wclke(w_wclke),
.we(w_we),
.byteen(w_byteen),
.waddr(addr),
.wdata(wdata),
.rclk(clk),
.re(w_re),
.raddr(addr),
.rdata(rdata),
//Titanium extra ports
.reset(w_reset), // reset
.waddren(w_addren), // write address enable
.raddren(w_addren) // read address enable
);
endmodule

4096
hw/efinix_fpga/ip/bram/init_bin.mem Normal file
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File diff suppressed because it is too large Load Diff

256
hw/efinix_fpga/ip/bram/init_hex.mem Normal file
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@@ -0,0 +1,256 @@
ea
4c
01
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1
hw/efinix_fpga/ip/bram/mem_config.txt Normal file
View File

@@ -0,0 +1 @@
[0, 8, 8, 8, 8, 256, 256, 1, 8, 1, 1, [[8, 20, 2, 0, 0], [9, 10, 1, 0, 0], [10, 5, 1, 0, 0], [8, 16, 2, 0, 1], [9, 8, 1, 0, 1], [10, 4, 1, 0, 1], [11, 2, 1, 0, 1], [12, 1, 1, 0, 1]], 1, [[0, 0, 1, 0, 0]], [[0, 0, 7, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 8, 20, 8, 20]], [], [], [], [], [], [], [], []]

6
hw/efinix_fpga/super6502.peri.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2022.1.226" db_version="20221999" last_change_date="Mon Dec 19 23:36:04 2022" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2022.1.226" db_version="20221999" last_change_date="Tue Dec 20 12:11:38 2022" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:device_info>
<efxpt:iobank_info>
<efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
@@ -69,8 +69,8 @@
<efxpt:gpio name="cpu_addr[9]" gpio_def="GPIOL_48" mode="input" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_addr[9]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_clk" gpio_def="GPIOL_71" mode="clkout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="" name_ddio_lo="" register_option="none" clock_name="clk_2" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
<efxpt:gpio name="cpu_clk" gpio_def="GPIOL_71" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="cpu_phi2" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_data[0]" gpio_def="GPIOL_68" mode="inout" bus_name="cpu_data" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_data_in[0]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>

20
hw/efinix_fpga/super6502.sv
View File

@@ -15,16 +15,21 @@ module super6502
output logic cpu_nmib,
output logic cpu_rdy,
output logic cpu_resb,
output logic pll_cpu_reset
output logic pll_cpu_reset,
output logic cpu_phi2
);
assign pll_cpu_reset = '1;
assign cpu_data_oe = '0;
assign cpu_data_oe = {8{cpu_rwb}};
assign cpu_rdy = '1;
assign cpu_irqb = '1;
assign cpu_nmib = '1;
always @(posedge clk_2) begin
cpu_phi2 <= ~cpu_phi2;
end
always @(posedge clk_2) begin
if (button_reset == '0) begin
cpu_resb <= '0;
@@ -36,4 +41,15 @@ always @(posedge clk_2) begin
end
end
efx_single_port_ram boot_rom(
.clk(clk_2), // clock input for one clock mode
.addr(cpu_addr[7:0]), // address input
.wclke('0), // Write clock-enable input
.byteen('0), // Byteen input
.we('0), // Write-enable input
.re(cpu_rwb), // Read-enable input
.rdata(cpu_data_out) // Read data output
);
endmodule

7
hw/efinix_fpga/super6502.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Mon December 19 2022 23:36:57" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.1.226" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project name="super6502" description="" last_change_date="Tue December 20 2022 15:37:23" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.1.226" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>
@@ -8,6 +8,11 @@
<efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008">
<efx:top_module name=""/>
<efx:design_file name="super6502.sv" version="default" library="default"/>
<efx:design_file name="ip/bram/bram_primitive.v" version="verilog_2k" library="default"/>
<efx:design_file name="ip/bram/bram_decompose.vh" version="verilog_2k" library="default"/>
<efx:design_file name="ip/bram/bram_ini.vh" version="verilog_2k" library="default"/>
<efx:design_file name="ip/bram/efx_single_port_ram.v" version="verilog_2k" library="default"/>
<efx:design_file name="ip/bram/bram_wrapper_mwm.v" version="verilog_2k" library="default"/>
<efx:top_vhdl_arch name=""/>
</efx:design_info>
<efx:constraint_info>