Merge from main

hw/efinix_fpga/simulation/Makefile

@@ -9,7 +9,8 @@ TEST_PROGRAM_NAME?=loop_test
 TEST_FOLDER?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)
 TEST_PROGRAM?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).hex
 
-STANDALONE_TB= interrupt_controller_tb mapper_code_tb mapper_tb rtc_tb
+STANDALONE_TB= interrupt_controller_tb mapper_tb rtc_tb
+CODE_TB= interrupt_controller_code_tb mapper_code_tb
 
 #TODO implement something like sources.list
 
@@ -34,13 +35,14 @@ full_sim: $(TARGET) $(SD_IMAGE)
 $(STANDALONE_TB): $(SRCS) $(TBS)
 	iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) tbs/$@.sv
 
-# mapper_code_tb: $(SRCS) $(TBS) $(INIT_MEM)
-# 	iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) $(TBS)
+$(CODE_TB): $(SRCS) $(TBS) $(INIT_MEM)
+	iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) tbs/$@.sv
 
 
 $(TARGET): $(INIT_MEM) $(SRCS)
 	iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
 
+.PHONY: $(INIT_MEM)
 $(INIT_MEM):
 # Make kernel
 	$(MAKE) -C $(REPO_TOP)/sw/kernel
@@ -58,4 +60,5 @@ clean:
 	rm -rf $(INIT_MEM)
 	rm -rf $(SD_IMAGE)
 	rm -rf $(STANDALONE_TB)
+	rm -rf $(CODE_TB)
 	rm -rf *.vcd

hw/efinix_fpga/simulation/src/sim_top.sv

@@ -61,6 +61,7 @@ logic w_cpu_reset;
 logic [15:0] w_cpu_addr;
 logic [7:0] w_cpu_data_from_cpu, w_cpu_data_from_dut;
 logic w_cpu_rdy;
+logic w_cpu_irqb;
 logic w_cpu_we;
 logic w_cpu_phi2;
 
@@ -70,7 +71,7 @@ cpu_65c02 u_cpu(
     .reset(~w_cpu_reset),
     .AB(w_cpu_addr),
     .RDY(w_cpu_rdy),
-    .IRQ('0),
+    .IRQ(~w_cpu_irqb),
     .NMI('0),
     .DI_s1(w_cpu_data_from_dut),
     .DO(w_cpu_data_from_cpu),
@@ -114,6 +115,7 @@ super6502 u_dut(
     .cpu_rwb(~w_cpu_we),
     .cpu_rdy(w_cpu_rdy),
     .cpu_phi2(w_cpu_phi2),
+    .cpu_irqb(w_cpu_irqb),
 
     .uart_rx(w_dut_uart_rx),
     .uart_tx(w_dut_uart_tx),

hw/efinix_fpga/simulation/tbs/interrupt_controller_code_tb.sv

@@ -0,0 +1,39 @@
+`timescale 1ns/1ps
+
+module interrupt_controller_code_tb();
+
+sim_top u_sim_top();
+
+always begin
+    if (
+        u_sim_top.w_cpu_addr == 16'h0 &&
+        u_sim_top.w_cpu_we == '1
+    ) begin
+        if (u_sim_top.w_cpu_data_from_cpu == 8'h6d) begin
+            $display("Good finish!");
+            $finish();
+        end else begin
+            $display("Bad finish!");
+            $finish_and_return(-1);
+        end
+    end
+    # 1;
+end
+
+initial begin
+    u_sim_top.u_dut.int_in = 0;
+    repeat (2400) @(posedge u_sim_top.r_clk_cpu);
+    for (int i = 0; i < 256; i++) begin
+        repeat (100) @(posedge u_sim_top.r_clk_cpu);
+        u_sim_top.u_dut.int_in = 1 << i;
+        $display("Activiating interrupt %d", i);
+    end
+end
+
+initial begin
+    repeat (40000) @(posedge u_sim_top.r_clk_cpu);
+    $display("Timed out");
+    $finish_and_return(-1);
+end
+
+endmodule

hw/efinix_fpga/src/super6502.sv

@@ -82,6 +82,7 @@ logic w_multiplier_cs;
 logic w_divider_cs;
 logic w_uart_cs;
 logic w_spi_cs;
+logic w_irq_cs;
 
 
 logic [7:0] w_rom_data_out;
@@ -91,6 +92,7 @@ logic [7:0] w_multiplier_data_out;
 logic [7:0] w_divider_data_out;
 logic [7:0] w_uart_data_out;
 logic [7:0] w_spi_data_out;
+logic [7:0] w_irq_data_out;
 logic [7:0] w_sdram_data_out;
 
 logic [24:0] w_mapped_addr;
@@ -99,6 +101,7 @@ always_comb begin
     w_mapper_cs = cpu_addr >= 16'h200 && cpu_addr <= 16'h21f;
 
     w_rom_cs = w_mapped_addr >= 16'hf000 && w_mapped_addr <= 16'hffff;
+    w_irq_cs = w_mapped_addr >= 16'heffc && w_mapped_addr <= 16'heffd;
     w_timer_cs = w_mapped_addr >= 16'heff8 && w_mapped_addr <= 16'heffb;
     w_multiplier_cs = w_mapped_addr >= 16'heff0 && w_mapped_addr <= 16'heff7;
     w_divider_cs = w_mapped_addr >= 16'hefe8 && w_mapped_addr <= 16'hefef;
@@ -113,7 +116,8 @@ always_comb begin
         w_divider_cs | 
         w_uart_cs | 
         w_spi_cs |
-        w_leds_cs  
+        w_leds_cs |
+        w_irq_cs 
     );
 
 
@@ -133,6 +137,8 @@ always_comb begin
         cpu_data_out = w_uart_data_out;
     else if (w_spi_cs)
         cpu_data_out = w_spi_data_out;
+    else if (w_irq_cs)
+        cpu_data_out = w_irq_data_out;
     else if (w_sdram_cs)
         cpu_data_out = w_sdram_data_out;
     else
@@ -261,13 +267,20 @@ sdram_adapter u_sdram_adapter(
     .o_sdr_DQM(o_sdr_DQM)
 );
 
+logic w_irq;
+assign cpu_irqb = ~w_irq;
+logic [255:0] int_in;
+
 interrupt_controller u_interrupt_controller(
     .clk(clk_cpu),
     .reset(~cpu_resb),
     .i_data(cpu_data_in),
     .o_data(w_irq_data_out),
+    .addr(w_mapped_addr[0]),
     .cs(w_irq_cs),
-    .rwb(cpu_rwb)
+    .rwb(cpu_rwb),
+    .int_in(int_in),
+    .int_out(w_irq)
 );