Byron Lathi 5433b4c6dc Merge from main

2023-11-18 17:41:59 -08:00

doc

Implement RTC

2023-11-17 21:51:09 -08:00

hw

Merge from main

2023-11-18 17:41:59 -08:00

sw

Check all edge interrupts

2023-11-18 15:00:44 -08:00

.gitignore

Start spi controller and tb

2023-07-21 22:10:39 -07:00

.gitlab-ci.yml

Add toolchain dependency to sim

2023-11-18 15:09:33 -08:00

.gitmodules

Resolve "Use dependencies instead of makefile chaining"

2023-09-30 04:16:52 +00:00

init_env.sh

Resolve "Run simulation as part of ci"

2023-09-30 05:05:12 +00:00

Description

No description provided

5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%