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Remove inferred latches

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This commit is contained in:
Byron Lathi
2024-10-13 19:50:02 -07:00
parent 6265a8090c
commit 5e8d91be53
9 changed files with 53 additions and 6 deletions
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2
hw/super6502_fpga/src/sub/my-fifos

Submodule hw/super6502_fpga/src/sub/my-fifos updated: a19156c9cd...8d960ab4bf

2
hw/super6502_fpga/src/sub/network_processor/src/tcp.sv
View File

@@ -205,6 +205,8 @@ logic [$clog2(NUM_TCP)-1:0] tcp_demux_sel;
logic [15:0] tcp_dests [NUM_TCP];
always_comb begin : TCP_DEST_SEL
tcp_demux_sel = '0;
for (int i = 0; i < NUM_TCP; i++) begin
if (tcp_dest == tcp_dests[i]) begin
tcp_demux_sel = i;

9
hw/super6502_fpga/src/sub/network_processor/src/tcp_dest_decap.sv
View File

@@ -100,6 +100,15 @@ always_comb begin
s_ip.ip_payload_axis_tready = '0;
valid = '0;
m_ip.ip_payload_axis_tdata = '0;
m_ip.ip_payload_axis_tvalid = '0;
m_ip.ip_payload_axis_tlast = '0;
m_ip.ip_payload_axis_tuser = '0;
m_ip.ip_payload_axis_tid = '0;
m_ip.ip_payload_axis_tdest = '0;
case (state)
PORTS: begin
s_ip.ip_payload_axis_tready = 1;

24
hw/super6502_fpga/src/sub/network_processor/src/tcp_packet_generator.sv
View File

@@ -92,9 +92,31 @@ always_ff @(posedge i_clk) begin
end
always_comb begin
state_next = state;
m_ip.ip_hdr_valid = '0;
m_ip.ip_dscp = '0;
m_ip.ip_ecn = '0;
m_ip.ip_length = '0;
m_ip.ip_ttl = '0;
m_ip.ip_protocol = '0;
m_ip.ip_source_ip = '0;
m_ip.ip_dest_ip = '0;
m_ip.ip_payload_axis_tdata = '0;
m_ip.ip_payload_axis_tvalid = '0;
m_ip.ip_payload_axis_tlast = '0;
m_ip.ip_payload_axis_tlast = '0;
m_ip.ip_payload_axis_tuser = '0;
m_ip.ip_payload_axis_tid = '0;
m_ip.ip_payload_axis_tdest = '0;
post_checksum_data.tready = '0;
checksum_counter_next = checksum_counter;
checksum_data = '0;
counter_next = counter;
o_packet_done = '0;
checksum_clear = '0;
checksum_enable = '0;

7
hw/super6502_fpga/src/sub/network_processor/src/tcp_parser.sv
View File

@@ -66,6 +66,13 @@ always_comb begin
checksum_next = checksum;
hdr_valid = '0;
counter_next = counter;
state_next = state;
s_ip.ip_hdr_ready = '0;
s_ip.ip_payload_axis_tready = '0;
case (state)
HEADER: begin
s_ip.ip_hdr_ready = '1;

5
hw/super6502_fpga/src/sub/network_processor/src/tcp_rx_ctrl.sv
View File

@@ -38,6 +38,11 @@ always_ff @(posedge i_clk) begin
end
always_comb begin
rx_msg_next = RX_MSG_NOP;
rx_msg_valid_next = '0;
ack_num_next = ack_num;
if (i_hdr_valid) begin
if (i_flags == 8'h12) begin
rx_msg_next = RX_MSG_RECV_SYNACK;

6
hw/super6502_fpga/src/sub/network_processor/src/tcp_tx_ctrl.sv
View File

@@ -25,8 +25,8 @@ module tcp_tx_ctrl(
);
axis_pipeline_register_wrapper u_m2s_reg (
.clk(clk),
.rst(rst),
.clk(i_clk),
.rst(i_rst),
.s_axis(s_axis),
.m_axis(m_axis)
@@ -60,6 +60,8 @@ always_comb begin
state_next = state;
o_no_data = '0;
o_tx_ctrl_ack = '0;
o_ack_number = '0;
o_flags = '0;
o_window_size = 16'h100;

2
hw/super6502_fpga/src/sub/stream_dmas

Submodule hw/super6502_fpga/src/sub/stream_dmas updated: 92ef12aed9...cbd06e5af4

2
hw/super6502_fpga/super6502_fpga.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502_fpga" description="" last_change="1728870039" sw_version="2024.1.163" last_run_state="pass" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project name="super6502_fpga" description="" last_change="1728874118" sw_version="2024.1.163" last_run_state="pass" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>