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Add divider

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Adds a 16x16 divider to go with the multiplier.

The divider is a single stage with no pipelining, which works at the
slow 2MHz frequency. Doing this lowers the maximum clock frequency to 5.

This is acceptable for now but means that the cpu can't be run at 14,
which is the maximum frequency.
This commit is contained in:
Byron Lathi
2023-01-05 18:35:42 -05:00
parent 42ad901ba4
commit 5f6657a227
14 changed files with 1585 additions and 438 deletions
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4
hw/efinix_fpga/ip/bram/bram_ini.vh
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@@ -4,8 +4,8 @@ input integer index;//Mode type
input integer val_; //Port A index, Port B Index, Number of Items in Loop, Port A Start, Port B Start, reserved
case (index)
0: bram_ini_table=
(val_== 0)?256'h008d000c8000a9000ef000f10008d00000000a9000ef000f00008d0007b000a9:
(val_== 1)?256'h0ef000ff0008d000ef000f5000ad000ef000f30008d00001000a9000ef000f20:
(val_== 0)?256'h008d0000d000a9000ef000e90008d00001000a9000ef000e80008d000c8000a9:
(val_== 1)?256'h0ef000ff0008d000ef000ec000ad000ef000eb0008d00000000a9000ef000ea0:
(val_== 2)?256'h00000000000000000000000000000000000000000000000000e300080000cb00:
(val_== 3)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_== 4)?256'h0000000000000000000000000000000000000000000000000000000000000000: