bslathi19/super6502
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Add high pair of seven segment displays

Browse Source 
This also increases the number of registers to 4, one more for the high
pair of displays, and a final one for a mask register which has not been
implemented yet.
This commit is contained in:
Byron Lathi
2022-03-12 21:24:37 -06:00
parent b4ff993080
commit 627b6a746a
5 changed files with 144 additions and 111 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
hw/fpga/SevenSeg.sv
View File

@@ -6,12 +6,12 @@ module SevenSeg(
input [7:0] data,
input cs,
input addr,
input [1:0] addr,
output logic [6:0] HEX0, HEX1, HEX2, HEX3
output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5
);
logic [7:0] _data [2];
logic [7:0] _data [3:0];
always_ff @(posedge clk) begin
if (rst)
@@ -21,12 +21,13 @@ always_ff @(posedge clk) begin
end
logic [3:0] hex_4[3:0];
logic [3:0] hex_4[5:0];
assign {hex_4[5], hex_4[4]} = _data[2];
assign {hex_4[3], hex_4[2]} = _data[1];
assign {hex_4[1], hex_4[0]} = _data[0];
HexDriver hex_drivers[3:0] (hex_4, {HEX3, HEX2, HEX1, HEX0});
HexDriver hex_drivers[5:0] (hex_4, {HEX5, HEX4, HEX3, HEX2, HEX1, HEX0});
endmodule