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Reset renaming, set card_detect

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This commit is contained in:
Byron Lathi
2024-07-17 00:43:30 -07:00
parent 6b7f7837dd
commit 63edbff30f
4 changed files with 20 additions and 17 deletions
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29
hw/super6502_fpga/src/rtl/super_6502_fpga.sv
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@@ -4,7 +4,7 @@ module super6502_fpga(
input logic i_tACclk, // t_ac clock (200MHz)
input clk_cpu,
input button_reset,
input button_resetn,
input pll_cpu_locked,
output logic pll_cpu_reset,
@@ -60,23 +60,26 @@ assign o_clk_phi2 = clk_cpu;
assign o_cpu0_data_oe = {8{i_cpu0_rwb}};
logic vio0_reset;
assign vio0_reset = '1;
logic vio0_resetn;
assign vio0_resetn = '1;
logic master_reset;
logic master_resetn;
logic sdram_ready;
logic [3:0] w_sdr_state;
logic pre_reset;
logic pre_resetn;
assign pre_reset = button_reset & vio0_reset;
assign pre_resetn = button_resetn & vio0_resetn;
assign sdram_ready = |w_sdr_state;
assign master_reset = pre_reset & sdram_ready;
assign master_resetn = pre_resetn & sdram_ready;
assign o_sd_cs = '1;
logic i_sd_cd;
assign i_sd_cd = '1;
logic cpu0_AWVALID;
logic cpu0_AWREADY;
@@ -194,7 +197,7 @@ logic [1:0] sd_controller_dma_RRESP;
cpu_wrapper u_cpu_wrapper_0(
.i_clk_cpu (clk_cpu),
.i_clk_100 (i_sysclk),
.i_rst (~master_reset),
.i_rst (~master_resetn),
.o_cpu_rst (o_cpu0_reset),
.o_cpu_rdy (o_cpu0_rdy),
@@ -246,7 +249,7 @@ axilxbar #(
})
) u_crossbar (
.S_AXI_ACLK (i_sysclk),
.S_AXI_ARESETN (master_reset),
.S_AXI_ARESETN (master_resetn),
.S_AXI_ARADDR ({cpu0_ARADDR, sd_controller_dma_ARADDR }),
.S_AXI_ARVALID ({cpu0_ARVALID, sd_controller_dma_ARVALID }),
@@ -290,7 +293,7 @@ axi4_lite_rom #(
.ROM_INIT_FILE("init_hex.mem")
) u_rom (
.i_clk(i_sysclk),
.i_rst(~master_reset),
.i_rst(~master_resetn),
.o_AWREADY(rom_awready),
.o_WREADY(rom_wready),
@@ -322,7 +325,7 @@ axi4_lite_ram #(
.RAM_SIZE(9)
) u_ram(
.i_clk(i_sysclk),
.i_rst(~master_reset),
.i_rst(~master_resetn),
.o_AWREADY(ram_awready),
.o_WREADY(ram_wready),
@@ -373,7 +376,7 @@ assign o_sdr_DATA_oe = w_sdr_DATA_oe[0+:16];
assign o_sdr_DQM = w_sdr_DQM[0+:2];
sdram_controller u_sdram_controller(
.i_aresetn (pre_reset),
.i_aresetn (pre_resetn),
.i_sysclk (i_sysclk),
.i_sdrclk (i_sdrclk),
.i_tACclk (i_tACclk),
@@ -436,7 +439,7 @@ sdio_top #(
.OPT_1P8V (0) // doesn't really matter but we don't need it
) u_sdio_top (
.i_clk (i_sysclk),
.i_reset (~master_reset),
.i_reset (~master_resetn),
.i_hsclk ('0), // Not using serdes
.S_AXIL_AWVALID (sd_controller_ctrl_AWVALID),

2
hw/super6502_fpga/src/sub/sdspi

Submodule hw/super6502_fpga/src/sub/sdspi updated: 78c24b8d58...f10a377dce

4
hw/super6502_fpga/super6502_fpga.peri.xml
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@@ -18,8 +18,8 @@
</efxpt:ctrl_info>
</efxpt:device_info>
<efxpt:gpio_info device_def="T20F256">
<efxpt:gpio name="button_reset" gpio_def="GPIOL_02" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="button_reset" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:gpio name="button_resetn" gpio_def="GPIOL_02" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="button_resetn" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_data[0]" gpio_def="GPIOL_68" mode="inout" bus_name="cpu_data" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_cpu0_data_from_cpu[0]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>

2
hw/super6502_fpga/super6502_fpga.xml
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502_fpga" description="" last_change_date="Wed July 17 2024 00:15:15" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project name="super6502_fpga" description="" last_change_date="Wed July 17 2024 00:42:05" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>