Use ZipCPU SD controller
I trust it more than the other one
This commit is contained in:
Byron Lathi
9
.gitmodules
vendored
9
.gitmodules
vendored
@@ -1,9 +1,6 @@
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[submodule "hw/super6502_fpga/src/sub/rtl-common"]
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path = hw/super6502_fpga/src/sub/rtl-common
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url = ../rtl-common.git
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[submodule "hw/super6502_fpga/src/sub/axi_crossbar"]
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path = hw/super6502_fpga/src/sub/axi_crossbar
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url = ../axi_crossbar.git
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[submodule "sw/toolchain/cc65"]
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path = sw/toolchain/cc65
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url = ../cc65.git
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@@ -16,6 +13,6 @@
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[submodule "hw/super6502_fpga/src/sub/wb2axip"]
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path = hw/super6502_fpga/src/sub/wb2axip
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url = ../wb2axip.git
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[submodule "hw/super6502_fpga/src/sub/sdcard_mass_storage_controller"]
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path = hw/super6502_fpga/src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller
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url = ../sdcard_mass_storage_controller.git
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[submodule "hw/super6502_fpga/src/sub/sdspi"]
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path = hw/super6502_fpga/src/sub/sdspi
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url = git@git.byronlathi.com:bslathi19/sdspi.git
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@@ -1,9 +1,4 @@
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src/rtl/super_6502_fpga.sv
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src/sub/axi_crossbar/src/rtl/axi_crossbar.sv
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src/sub/axi_crossbar/src/rtl/axi_master.sv
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src/sub/axi_crossbar/src/rtl/axi_slave.sv
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src/sub/axi_crossbar/src/rtl/rr_scheduler.sv
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src/sub/axi_crossbar/src/rtl/slave_addr_decoder.sv
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src/sub/cpu_wrapper/cpu_wrapper.sv
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src/sub/rtl-common/src/rtl/async_fifo.sv
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src/sub/rtl-common/src/rtl/axi4_lite_ram.sv
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@@ -43,8 +43,8 @@ module super6502_fpga(
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input i_sd_dat,
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output o_sd_dat,
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output o_sd_dat_oe,
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output o_sd_clk,
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output o_sd_cs
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output o_sd_clk
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// input i_sd_cd
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);
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@@ -153,23 +153,23 @@ logic [1:0] sdram_RRESP;
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// These are for the control/status registers
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logic sd_controller_csr_AWVALID;
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logic sd_controller_csr_AWREADY;
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logic [ADDR_WIDTH-1:0] sd_controller_csr_AWADDR;
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logic sd_controller_csr_WVALID;
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logic sd_controller_csr_WREADY;
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logic [DATA_WIDTH-1:0] sd_controller_csr_WDATA;
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logic [DATA_WIDTH/8-1:0] sd_controller_csr_WSTRB;
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logic sd_controller_csr_BVALID;
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logic sd_controller_csr_BREADY;
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logic [1:0] sd_controller_csr_BRESP;
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logic sd_controller_csr_ARVALID;
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logic sd_controller_csr_ARREADY;
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logic [ADDR_WIDTH-1:0] sd_controller_csr_ARADDR;
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logic sd_controller_csr_RVALID;
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logic sd_controller_csr_RREADY;
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logic [DATA_WIDTH-1:0] sd_controller_csr_RDATA;
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logic [1:0] sd_controller_csr_RRESP;
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logic sd_controller_ctrl_AWVALID;
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logic sd_controller_ctrl_AWREADY;
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logic [ADDR_WIDTH-1:0] sd_controller_ctrl_AWADDR;
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logic sd_controller_ctrl_WVALID;
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logic sd_controller_ctrl_WREADY;
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logic [DATA_WIDTH-1:0] sd_controller_ctrl_WDATA;
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logic [DATA_WIDTH/8-1:0] sd_controller_ctrl_WSTRB;
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logic sd_controller_ctrl_BVALID;
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logic sd_controller_ctrl_BREADY;
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logic [1:0] sd_controller_ctrl_BRESP;
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logic sd_controller_ctrl_ARVALID;
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logic sd_controller_ctrl_ARREADY;
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logic [ADDR_WIDTH-1:0] sd_controller_ctrl_ARADDR;
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logic sd_controller_ctrl_RVALID;
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logic sd_controller_ctrl_RREADY;
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logic [DATA_WIDTH-1:0] sd_controller_ctrl_RDATA;
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logic [1:0] sd_controller_ctrl_RRESP;
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// these are for the dma master.
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logic sd_controller_dma_AWVALID;
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@@ -235,47 +235,53 @@ cpu_wrapper u_cpu_wrapper_0(
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);
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axi_crossbar #(
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.N_INITIATORS(2),
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.N_TARGETS(4)
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axilxbar #(
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.NM(2),
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.NS(4),
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.SLAVE_ADDR({
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{32'h000001ff, 32'h00000000},
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{32'h0000ffff, 32'h0000ff00},
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{32'h0000dfff, 32'h00000200},
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{32'h0000e03f, 32'h0000e000}
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})
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) u_crossbar (
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.clk(i_sysclk),
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.rst(~master_reset),
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.S_AXI_ACLK (i_sysclk),
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.S_AXI_ARESETN (master_reset),
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.ini_araddr ({cpu0_ARADDR, sd_controller_dma_ARADDR }),
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.ini_arvalid ({cpu0_ARVALID, sd_controller_dma_ARVALID }),
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.ini_arready ({cpu0_ARREADY, sd_controller_dma_ARREADY }),
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.ini_rdata ({cpu0_RDATA, sd_controller_dma_RDATA }),
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.ini_rresp ({cpu0_RRESP, sd_controller_dma_RRESP }),
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.ini_rvalid ({cpu0_RVALID, sd_controller_dma_RVALID }),
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.ini_rready ({cpu0_RREADY, sd_controller_dma_RREADY }),
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.ini_awaddr ({cpu0_AWADDR, sd_controller_dma_AWADDR }),
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.ini_awready ({cpu0_AWREADY, sd_controller_dma_AWREADY }),
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.ini_awvalid ({cpu0_AWVALID, sd_controller_dma_AWVALID }),
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.ini_wvalid ({cpu0_WVALID, sd_controller_dma_WVALID }),
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.ini_wready ({cpu0_WREADY, sd_controller_dma_WREADY }),
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.ini_wdata ({cpu0_WDATA, sd_controller_dma_WDATA }),
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.ini_wstrb ({cpu0_WSTRB, sd_controller_dma_WSTRB }),
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.ini_bresp ({cpu0_BRESP, sd_controller_dma_BRESP }),
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.ini_bvalid ({cpu0_BVALID, sd_controller_dma_BVALID }),
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.ini_bready ({cpu0_BREADY, sd_controller_dma_BREADY }),
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.tgt_araddr ({ram_araddr, rom_araddr, sdram_ARADDR, sd_controller_csr_ARADDR }),
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.tgt_arvalid ({ram_arvalid, rom_arvalid, sdram_ARVALID, sd_controller_csr_ARVALID }),
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.tgt_arready ({ram_arready, rom_arready, sdram_ARREADY, sd_controller_csr_ARREADY }),
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.tgt_rdata ({ram_rdata, rom_rdata, sdram_RDATA, sd_controller_csr_RDATA }),
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.tgt_rresp ({ram_rresp, rom_rresp, sdram_RRESP, sd_controller_csr_RRESP }),
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.tgt_rvalid ({ram_rvalid, rom_rvalid, sdram_RVALID, sd_controller_csr_RVALID }),
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.tgt_rready ({ram_rready, rom_rready, sdram_RREADY, sd_controller_csr_RREADY }),
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.tgt_awaddr ({ram_awaddr, rom_awaddr, sdram_AWADDR, sd_controller_csr_AWADDR }),
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.tgt_awvalid ({ram_awvalid, rom_awvalid, sdram_AWVALID, sd_controller_csr_AWVALID }),
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.tgt_awready ({ram_awready, rom_awready, sdram_AWREADY, sd_controller_csr_AWREADY }),
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.tgt_wdata ({ram_wdata, rom_wdata, sdram_WDATA, sd_controller_csr_WDATA }),
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.tgt_wvalid ({ram_wvalid, rom_wvalid, sdram_WVALID, sd_controller_csr_WVALID }),
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.tgt_wready ({ram_wready, rom_wready, sdram_WREADY, sd_controller_csr_WREADY }),
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.tgt_wstrb ({ram_wstrb, rom_wstrb, sdram_WSTRB, sd_controller_csr_WSTRB }),
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.tgt_bresp ({ram_bresp, rom_bresp, sdram_BRESP, sd_controller_csr_BRESP }),
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.tgt_bvalid ({ram_bvalid, rom_bvalid, sdram_BVALID, sd_controller_csr_BVALID }),
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.tgt_bready ({ram_bready, rom_bready, sdram_BREADY, sd_controller_csr_BREADY })
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.S_AXI_ARADDR ({cpu0_ARADDR, sd_controller_dma_ARADDR }),
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.S_AXI_ARVALID ({cpu0_ARVALID, sd_controller_dma_ARVALID }),
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.S_AXI_ARREADY ({cpu0_ARREADY, sd_controller_dma_ARREADY }),
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.S_AXI_RDATA ({cpu0_RDATA, sd_controller_dma_RDATA }),
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.S_AXI_RRESP ({cpu0_RRESP, sd_controller_dma_RRESP }),
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.S_AXI_RVALID ({cpu0_RVALID, sd_controller_dma_RVALID }),
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.S_AXI_RREADY ({cpu0_RREADY, sd_controller_dma_RREADY }),
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.S_AXI_AWADDR ({cpu0_AWADDR, sd_controller_dma_AWADDR }),
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.S_AXI_AWREADY ({cpu0_AWREADY, sd_controller_dma_AWREADY }),
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.S_AXI_AWVALID ({cpu0_AWVALID, sd_controller_dma_AWVALID }),
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.S_AXI_WVALID ({cpu0_WVALID, sd_controller_dma_WVALID }),
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.S_AXI_WREADY ({cpu0_WREADY, sd_controller_dma_WREADY }),
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.S_AXI_WDATA ({cpu0_WDATA, sd_controller_dma_WDATA }),
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.S_AXI_WSTRB ({cpu0_WSTRB, sd_controller_dma_WSTRB }),
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.S_AXI_BRESP ({cpu0_BRESP, sd_controller_dma_BRESP }),
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.S_AXI_BVALID ({cpu0_BVALID, sd_controller_dma_BVALID }),
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.S_AXI_BREADY ({cpu0_BREADY, sd_controller_dma_BREADY }),
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.M_AXI_ARADDR ({ram_araddr, rom_araddr, sdram_ARADDR, sd_controller_ctrl_ARADDR }),
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.M_AXI_ARVALID ({ram_arvalid, rom_arvalid, sdram_ARVALID, sd_controller_ctrl_ARVALID }),
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.M_AXI_ARREADY ({ram_arready, rom_arready, sdram_ARREADY, sd_controller_ctrl_ARREADY }),
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.M_AXI_RDATA ({ram_rdata, rom_rdata, sdram_RDATA, sd_controller_ctrl_RDATA }),
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.M_AXI_RRESP ({ram_rresp, rom_rresp, sdram_RRESP, sd_controller_ctrl_RRESP }),
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.M_AXI_RVALID ({ram_rvalid, rom_rvalid, sdram_RVALID, sd_controller_ctrl_RVALID }),
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.M_AXI_RREADY ({ram_rready, rom_rready, sdram_RREADY, sd_controller_ctrl_RREADY }),
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.M_AXI_AWADDR ({ram_awaddr, rom_awaddr, sdram_AWADDR, sd_controller_ctrl_AWADDR }),
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.M_AXI_AWVALID ({ram_awvalid, rom_awvalid, sdram_AWVALID, sd_controller_ctrl_AWVALID }),
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.M_AXI_AWREADY ({ram_awready, rom_awready, sdram_AWREADY, sd_controller_ctrl_AWREADY }),
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.M_AXI_WDATA ({ram_wdata, rom_wdata, sdram_WDATA, sd_controller_ctrl_WDATA }),
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.M_AXI_WVALID ({ram_wvalid, rom_wvalid, sdram_WVALID, sd_controller_ctrl_WVALID }),
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.M_AXI_WREADY ({ram_wready, rom_wready, sdram_WREADY, sd_controller_ctrl_WREADY }),
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.M_AXI_WSTRB ({ram_wstrb, rom_wstrb, sdram_WSTRB, sd_controller_ctrl_WSTRB }),
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.M_AXI_BRESP ({ram_bresp, rom_bresp, sdram_BRESP, sd_controller_ctrl_BRESP }),
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.M_AXI_BVALID ({ram_bvalid, rom_bvalid, sdram_BVALID, sd_controller_ctrl_BVALID }),
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.M_AXI_BREADY ({ram_bready, rom_bready, sdram_BREADY, sd_controller_ctrl_BREADY })
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);
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@@ -417,51 +423,72 @@ sdram_controller u_sdram_controller(
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.o_sdr_DQM (w_sdr_DQM)
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);
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logic sd_controller_apb_psel;
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logic sd_controller_apb_penable;
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logic sd_controller_apb_pwrite;
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logic [2:0] sd_controller_apb_pprot;
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logic [ADDR_WIDTH-1:0] sd_controller_apb_paddr;
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logic [DATA_WIDTH-1:0] sd_controller_apb_pwdata;
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logic [DATA_WIDTH/8-1:0] sd_controller_apb_pstrb;
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logic sd_controller_apb_pready;
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logic [DATA_WIDTH-1:0] sd_controller_apb_prdata;
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logic sd_controller_apb_pslverr;
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logic sd_irq;
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sdio_top #(
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.NUMIO (1), // board as it stands is in 1 bit mode
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.ADDRESS_WIDTH (32),
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.DW (32),
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.OPT_DMA (1),
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.OPT_EMMC (0),
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.OPT_SERDES (0),
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.OPT_DDR (0),
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.OPT_1P8V (0) // doesn't really matter but we don't need it
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) u_sdio_top (
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.i_clk (i_sysclk),
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.i_reset (~master_reset),
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.i_hsclk ('0), // Not using serdes
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axi4_lite_to_apb4 u_sd_axi_apb_converter (
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.i_clk(i_sysclk),
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.i_rst(~master_reset),
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.S_AXIL_AWVALID (sd_controller_ctrl_AWVALID),
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.S_AXIL_AWREADY (sd_controller_ctrl_AWREADY),
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.S_AXIL_AWADDR (sd_controller_ctrl_AWADDR),
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.S_AXIL_AWPROT ('0),
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.S_AXIL_WVALID (sd_controller_ctrl_WVALID),
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.S_AXIL_WREADY (sd_controller_ctrl_WREADY),
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.S_AXIL_WDATA (sd_controller_ctrl_WDATA),
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.S_AXIL_WSTRB (sd_controller_ctrl_WSTRB),
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.S_AXIL_BVALID (sd_controller_ctrl_BVALID),
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.S_AXIL_BREADY (sd_controller_ctrl_BREADY),
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.S_AXIL_BRESP (sd_controller_ctrl_BRESP),
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.S_AXIL_ARVALID (sd_controller_ctrl_ARVALID),
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.S_AXIL_ARREADY (sd_controller_ctrl_ARREADY),
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.S_AXIL_ARADDR (sd_controller_ctrl_ARADDR),
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.S_AXIL_ARPROT ('0),
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.S_AXIL_RVALID (sd_controller_ctrl_RVALID),
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.S_AXIL_RREADY (sd_controller_ctrl_RREADY),
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.S_AXIL_RDATA (sd_controller_ctrl_RDATA),
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.S_AXIL_RRESP (sd_controller_ctrl_RRESP),
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.i_AWVALID(sd_controller_csr_AWVALID),
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.o_AWREADY(sd_controller_csr_AWREADY),
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.i_AWADDR(sd_controller_csr_AWADDR),
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.i_WVALID(sd_controller_csr_AWVALID),
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.o_WREADY(sd_controller_csr_WREADY),
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.i_WDATA(sd_controller_csr_WDATA),
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.i_WSTRB(sd_controller_csr_WSTRB),
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.o_BVALID(sd_controller_csr_BVALID),
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.i_BREADY(sd_controller_csr_BREADY),
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.o_BRESP(sd_controller_csr_BRESP),
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.i_ARVALID(sd_controller_csr_ARVALID),
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.o_ARREADY(sd_controller_csr_ARREADY),
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.i_ARADDR(sd_controller_csr_ARADDR),
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.i_ARPROT('0),
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.o_RVALID(sd_controller_csr_RVALID),
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.i_RREADY(sd_controller_csr_RREADY),
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.o_RDATA(sd_controller_csr_RDATA),
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.o_RRESP(sd_controller_csr_RRESP),
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.M_AXI_AWVALID (sd_controller_dma_AWVALID),
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.M_AXI_AWREADY (sd_controller_dma_AWREADY),
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.M_AXI_AWADDR (sd_controller_dma_AWADDR),
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.M_AXI_AWPROT (),
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.M_AXI_WVALID (sd_controller_dma_WVALID),
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.M_AXI_WREADY (sd_controller_dma_WREADY),
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.M_AXI_WDATA (sd_controller_dma_WDATA),
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.M_AXI_WSTRB (sd_controller_dma_WSTRB),
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.M_AXI_BVALID (sd_controller_dma_BVALID),
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.M_AXI_BREADY (sd_controller_dma_BREADY),
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.M_AXI_BRESP (sd_controller_dma_BRESP),
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.M_AXI_ARVALID (sd_controller_dma_ARVALID),
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.M_AXI_ARREADY (sd_controller_dma_ARREADY),
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.M_AXI_ARADDR (sd_controller_dma_ARADDR),
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.M_AXI_ARPROT (),
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.M_AXI_RVALID (sd_controller_dma_RVALID),
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.M_AXI_RREADY (sd_controller_dma_RREADY),
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.M_AXI_RDATA (sd_controller_dma_RDATA),
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.M_AXI_RRESP (sd_controller_dma_RRESP),
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.m_apb_psel(sd_controller_apb_psel),
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.m_apb_penable(sd_controller_apb_penable),
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.m_apb_pwrite(sd_controller_apb_pwrite),
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.m_apb_pprot(sd_controller_apb_pprot),
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.m_apb_paddr(sd_controller_apb_paddr),
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.m_apb_pwdata(sd_controller_apb_pwdata),
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.m_apb_pstrb(sd_controller_apb_pstrb),
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.m_apb_pready(sd_controller_apb_pready),
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.m_apb_prdata(sd_controller_apb_prdata),
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.m_apb_pslverr(sd_controller_apb_pslverr)
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.i_dat (i_sd_dat),
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.o_dat (o_sd_dat),
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.io_dat_tristate (o_sd_dat_oe),
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.i_cmd (i_sd_cmd),
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.o_cmd (o_sd_cmd),
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.io_cmd_tristate (o_sd_cmd_oe),
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.o_ck (o_sd_clk),
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.i_ds ('0), //emmc, don't care
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.i_card_detect (i_sd_cd),
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.o_int (sd_irq)
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);
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endmodule
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Submodule hw/super6502_fpga/src/sub/axi_crossbar deleted from 5c61f56e7b
@@ -1,215 +0,0 @@
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module sd_controller_wrapper(
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input i_clk_100,
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input i_rst_100,
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input logic i_ctrl_AWVALID,
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output logic o_ctrl_AWREADY,
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input logic [31:0] i_ctrl_AWADDR,
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input logic [2:0] i_ctrl_AWPROT,
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input logic i_ctrl_WVALID,
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output logic o_ctrl_WREADY,
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input logic [31:0] i_ctrl_WDATA,
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input logic [3:0] i_ctrl_WSTRB,
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output logic o_ctrl_BVALID,
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input logic i_ctrl_BREADY,
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output logic [1:0] o_ctrl_BRESP,
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input logic i_ctrl_ARVALID,
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output logic o_ctrl_ARREADY,
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input logic [31:0] i_ctrl_ARADDR,
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input logic [2:0] i_ctrl_ARPROT,
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output logic o_ctrl_RVALID,
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input logic i_ctrl_RREADY,
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output logic [31:0] o_ctrl_RDATA,
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output logic [1:0] o_ctrl_RRESP,
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||||
output logic o_dma_AWVALID,
|
||||
input logic i_dma_AWREADY,
|
||||
output logic [31:0] o_dma_AWADDR,
|
||||
output logic [2:0] o_dma_AWPROT,
|
||||
|
||||
output logic o_dma_WVALID,
|
||||
input logic i_dma_WREADY,
|
||||
output logic [31:0] o_dma_WDATA,
|
||||
output logic [31:0] o_dma_WSTRB,
|
||||
|
||||
input logic i_dma_BVALID,
|
||||
output logic o_dma_BREADY,
|
||||
input logic [1:0] i_dma_BRESP,
|
||||
|
||||
output logic o_dma_ARVALID,
|
||||
input logic i_dma_ARREADY,
|
||||
output logic [31:0] o_dma_ARADDR,
|
||||
output logic [2:0] o_dma_ARPROT,
|
||||
|
||||
input logic i_dma_RVALID,
|
||||
output logic o_dma_RREADY,
|
||||
input logic [31:0] i_dma_RDATA,
|
||||
input logic [1:0] i_dma_RRESP,
|
||||
|
||||
input wire [3:0] sd_dat_dat_i, //Data in from SDcard
|
||||
output wire [3:0] sd_dat_out_o, //Data out to SDcard
|
||||
output wire sd_dat_oe_o, //SD Card tristate Data Output enable (Connects on the SoC TopLevel)
|
||||
|
||||
input wire sd_cmd_dat_i, //Command in from SDcard
|
||||
output wire sd_cmd_out_o, //Command out to SDcard
|
||||
output wire sd_cmd_oe_o //SD Card tristate CMD Output enable (Connects on the SoC TopLevel)
|
||||
);
|
||||
|
||||
logic wb_reset;
|
||||
logic wb_clock;
|
||||
|
||||
logic [31:0] wb_ctrl_data_i;
|
||||
logic [31:0] wb_ctrl_data_o;
|
||||
logic [31:0] wb_ctrl_addr_i; // need to do address offset either here or in xbar
|
||||
logic [3:0] wb_ctrl_sel_i;
|
||||
logic wb_ctrl_we_i;
|
||||
logic wb_ctrl_cyc_i;
|
||||
logic wb_ctrl_stb_i;
|
||||
logic wb_ctrl_ack_o;
|
||||
|
||||
logic [31:0] wb_dma_adr_o;
|
||||
logic [3:0] wb_dma_sel_o;
|
||||
logic wb_dma_we_o;
|
||||
logic [31:0] wb_dma_dat_i;
|
||||
logic [31:0] wb_dma_dat_o;
|
||||
logic wb_dma_cyc_o;
|
||||
logic wb_dma_stb_o;
|
||||
logic wb_dma_ack_i;
|
||||
logic [2:0] wb_dma_cti_o;
|
||||
logic [1:0] wb_dma_bte_o;
|
||||
|
||||
|
||||
//axilite2wbsp
|
||||
axilite2wbsp #(
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.LGFIFO(4),
|
||||
.OPT_READONLY(0),
|
||||
.OPT_WRITEONLY(0)
|
||||
) u_axilite2wbsp (
|
||||
.i_clk (i_clk_100),
|
||||
.i_axi_reset_n (~i_rst_100),
|
||||
|
||||
.i_axi_awvalid (i_ctrl_AWVALID),
|
||||
.o_axi_awready (o_ctrl_AWREADY),
|
||||
.i_axi_awaddr (i_ctrl_AWADDR),
|
||||
.i_axi_awprot (i_ctrl_AWPROT),
|
||||
|
||||
.i_axi_wvalid (i_ctrl_AWVALID),
|
||||
.o_axi_wready (o_ctrl_WREADY),
|
||||
.i_axi_wdata (i_ctrl_WDATA),
|
||||
.i_axi_wstrb (i_ctrl_WSTRB),
|
||||
|
||||
.o_axi_bvalid (o_ctrl_BVALID),
|
||||
.i_axi_bready (i_ctrl_BREADY),
|
||||
.o_axi_bresp (o_ctrl_BRESP),
|
||||
|
||||
.i_axi_arvalid (i_ctrl_ARVALID),
|
||||
.o_axi_arready (o_ctrl_ARREADY),
|
||||
.i_axi_araddr (i_ctrl_ARADDR),
|
||||
.i_axi_arprot (i_ctrl_ARPROT),
|
||||
|
||||
.o_axi_rvalid (o_ctrl_RVALID),
|
||||
.i_axi_rready (i_ctrl_RREADY),
|
||||
.o_axi_rdata (o_ctrl_rdata),
|
||||
.o_axi_rresp (o_ctrl_rresp),
|
||||
|
||||
.o_reset (wb_reset),
|
||||
|
||||
.o_wb_cyc (wb_ctrl_cyc_i),
|
||||
.o_wb_stb (wb_ctrl_stb_i),
|
||||
.o_wb_we (wb_ctrl_we_i),
|
||||
.o_wb_addr (wb_ctrl_addr_i),
|
||||
.o_wb_data (wb_ctrl_data_i),
|
||||
.o_wb_sel (wb_ctrl_sel_i),
|
||||
.i_wb_stall ('0),
|
||||
.i_wb_ack (wb_ctrl_ack_o),
|
||||
.i_wb_data (wb_ctrl_data_o),
|
||||
.i_wb_err ('0)
|
||||
);
|
||||
|
||||
//wb2axilite
|
||||
wbm2axilite #(
|
||||
.C_AXI_ADDR_WIDTH(32)
|
||||
) u_wbm2axilite (
|
||||
.i_clk (i_clk_100),
|
||||
.i_reset (wb_reset),
|
||||
|
||||
.i_wb_cyc (wb_dma_cyc_o),
|
||||
.i_wb_stb (wb_dma_stb_o),
|
||||
.i_wb_we (wb_dma_we_o),
|
||||
.i_wb_addr (wb_dma_adr_o),
|
||||
.i_wb_data (wb_dma_dat_o),
|
||||
.i_wb_sel (wb_dma_sel_o),
|
||||
.o_wb_stall (),
|
||||
.o_wb_ack (wb_dma_ack_i),
|
||||
.o_wb_data (wb_dma_dat_i),
|
||||
.o_wb_err (),
|
||||
|
||||
.o_axi_awvalid (o_dma_AWVALID),
|
||||
.i_axi_awready (i_dma_AWREADY),
|
||||
.o_axi_awaddr (o_dma_AWADDR),
|
||||
.o_axi_awprot (o_dma_AWPROT),
|
||||
|
||||
.o_axi_wvalid (o_dma_WVALID),
|
||||
.i_axi_wready (i_dma_WREADY),
|
||||
.o_axi_wdata (o_dma_WDATA),
|
||||
.o_axi_wstrb (o_dma_WSTRB),
|
||||
|
||||
.i_axi_bvalid (i_dma_BVALID),
|
||||
.o_axi_bready (o_dma_BREADY),
|
||||
.i_axi_bresp (i_dma_BRESP),
|
||||
|
||||
.o_axi_arvalid (o_dma_ARVALID),
|
||||
.i_axi_arready (i_dma_ARREADY),
|
||||
.o_axi_araddr (o_dma_ARADDR),
|
||||
.o_axi_arprot (o_dma_ARPROT),
|
||||
|
||||
.i_axi_rvalid (i_dma_RVALID),
|
||||
.o_axi_rready (o_dma_RREADY),
|
||||
.i_axi_rdata (i_dma_RDATA),
|
||||
.i_axi_rresp (i_dma_RRESP)
|
||||
);
|
||||
|
||||
//sdc controller
|
||||
sdc_controller u_sdc_controller (
|
||||
.wb_clk_i (i_clk_100),
|
||||
.wb_rst_i (wb_reset),
|
||||
|
||||
.wb_dat_i (wb_ctrl_data_i),
|
||||
.wb_dat_o (wb_ctrl_data_o),
|
||||
.wb_adr_i (wb_ctrl_addr_i),
|
||||
.wb_sel_i (wb_ctrl_sel_i),
|
||||
.wb_we_i (wb_ctrl_we_i),
|
||||
.wb_cyc_i (wb_ctrl_cyc_i),
|
||||
.wb_stb_i (wb_ctrl_stb_i),
|
||||
.wb_ack_o (wb_ctrl_ack_o),
|
||||
|
||||
.m_wb_adr_o (wb_dma_adr_o),
|
||||
.m_wb_sel_o (wb_dma_sel_o),
|
||||
.m_wb_we_o (wb_dma_we_o),
|
||||
.m_wb_dat_o (wb_dma_dat_o),
|
||||
.m_wb_dat_i (wb_dma_dat_i),
|
||||
.m_wb_cyc_o (wb_dma_cyc_o),
|
||||
.m_wb_stb_o (wb_dma_stb_o),
|
||||
.m_wb_ack_i (wb_dma_ack_i),
|
||||
.m_wb_cti_o (), // uhh, guys?
|
||||
.m_wb_bte_o (),
|
||||
|
||||
.sd_cmd_dat_i (sd_cmd_i),
|
||||
.sd_cmd_dat_o (sd_cmd_o),
|
||||
.sd_cmd_oe_o (sd_cmd_oe),
|
||||
.sd_dat_dat_i (sd_dat_i),
|
||||
.sd_dat_dat_o (sd_dat_o),
|
||||
.sd_dat_oe_o (sd_dat_oe),
|
||||
|
||||
.card_detect (sd_cd),
|
||||
.sd_clk_o_pad (sd_clk)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
Submodule hw/super6502_fpga/src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller deleted from a9a5811c05
1
hw/super6502_fpga/src/sub/sdspi
Submodule
1
hw/super6502_fpga/src/sub/sdspi
Submodule
Submodule hw/super6502_fpga/src/sub/sdspi added at 78c24b8d58
@@ -1,115 +1,115 @@
|
||||
<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Tue Jul 16 2024 06:55:10 PM" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<efx:project name="super6502_fpga" description="" last_change_date="Wed July 17 2024 00:15:15" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
|
||||
<efx:device_info>
|
||||
<efx:family name="Trion" />
|
||||
<efx:device name="T20F256" />
|
||||
<efx:timing_model name="I4" />
|
||||
<efx:family name="Trion"/>
|
||||
<efx:device name="T20F256"/>
|
||||
<efx:timing_model name="I4"/>
|
||||
</efx:device_info>
|
||||
<efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008">
|
||||
<efx:top_module name="super6502_fpga" />
|
||||
<efx:design_file name="src/rtl/super_6502_fpga.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/cpu_wrapper/cpu_wrapper.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/rtl-common/src/rtl/axi4_lite_rom.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/rtl-common/src/rtl/axi4_lite_ram.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/rtl-common/src/rtl/ff_cdc.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/axi_crossbar/src/rtl/axi_master.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/axi_crossbar/src/rtl/axi_slave.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/axi_crossbar/src/rtl/slave_addr_decoder.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/axi_crossbar/src/rtl/axi_crossbar.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/axi_crossbar/src/rtl/rr_scheduler.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/rtl-common/src/rtl/axi4_lite_to_apb4.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/rtl-common/src/rtl/async_fifo.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_controller_wrapper.sv" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sdc_controller.v" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_cmd_master.v" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_crc_7.v" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_controller_wb.v" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_fifo_rx_filler.v" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_rx_fifo.v" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_cmd_serial_host.v" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_fifo_tx_filler.v" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_data_serial_host.v" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_data_master.v" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_rx_fifo_tb.v" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_bd.v" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_defines.v" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_tx_fifo.v" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_clock_divider.v" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_crc_16.v" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/wb2axip/rtl/axlite2wbsp.v" version="default" library="default" />
|
||||
<efx:design_file name="src/sub/wb2axip/rtl/wbm2axilite.v" version="default" library="default" />
|
||||
<efx:top_vhdl_arch name="" />
|
||||
<efx:top_module name="super6502_fpga"/>
|
||||
<efx:design_file name="src/rtl/super_6502_fpga.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/cpu_wrapper/cpu_wrapper.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/rtl-common/src/rtl/axi4_lite_rom.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/rtl-common/src/rtl/axi4_lite_ram.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/rtl-common/src/rtl/ff_cdc.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/rtl-common/src/rtl/axi4_lite_to_apb4.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/rtl-common/src/rtl/async_fifo.sv" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/wb2axip/rtl/axilxbar.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/wb2axip/rtl/addrdecode.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/wb2axip/rtl/skidbuffer.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/sdspi/rtl/sdckgen.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/sdspi/rtl/sddma_rxgears.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/sdspi/rtl/sddma.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/sdspi/rtl/sdrxframe.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/sdspi/rtl/sdtxframe.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/sdspi/rtl/sddma_s2mm.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/sdspi/rtl/afifo.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/sdspi/rtl/sddma_txgears.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/sdspi/rtl/sdskid.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/sdspi/rtl/sdfrontend.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/sdspi/rtl/spicmd.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/sdspi/rtl/sdaxil.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/sdspi/rtl/sddma_mm2s.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/sdspi/rtl/sdio_top.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/sdspi/rtl/sdwb.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/sdspi/rtl/sdio.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/sdspi/rtl/sdcmd.v" version="default" library="default"/>
|
||||
<efx:design_file name="src/sub/sdspi/rtl/sdfifo.v" version="default" library="default"/>
|
||||
<efx:top_vhdl_arch name=""/>
|
||||
</efx:design_info>
|
||||
<efx:constraint_info>
|
||||
<efx:sdc_file name="constraints/constraints.sdc" />
|
||||
<efx:inter_file name="" />
|
||||
<efx:sdc_file name="constraints/constraints.sdc"/>
|
||||
<efx:inter_file name=""/>
|
||||
</efx:constraint_info>
|
||||
<efx:sim_info />
|
||||
<efx:misc_info />
|
||||
<efx:sim_info/>
|
||||
<efx:misc_info/>
|
||||
<efx:ip_info>
|
||||
<efx:ip instance_name="sdram_controller" path="ip/sdram_controller/settings.json">
|
||||
<efx:ip_src_file name="sdram_controller.v" />
|
||||
<efx:ip_src_file name="sdram_controller.v"/>
|
||||
</efx:ip>
|
||||
</efx:ip_info>
|
||||
<efx:synthesis tool_name="efx_map">
|
||||
<efx:param name="work_dir" value="work_syn" value_type="e_string" />
|
||||
<efx:param name="write_efx_verilog" value="on" value_type="e_bool" />
|
||||
<efx:param name="allow-const-ram-index" value="0" value_type="e_option" />
|
||||
<efx:param name="blackbox-error" value="1" value_type="e_option" />
|
||||
<efx:param name="blast_const_operand_adders" value="1" value_type="e_option" />
|
||||
<efx:param name="bram_output_regs_packing" value="1" value_type="e_option" />
|
||||
<efx:param name="create-onehot-fsms" value="0" value_type="e_option" />
|
||||
<efx:param name="fanout-limit" value="0" value_type="e_integer" />
|
||||
<efx:param name="hdl-compile-unit" value="1" value_type="e_option" />
|
||||
<efx:param name="infer-clk-enable" value="3" value_type="e_option" />
|
||||
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option" />
|
||||
<efx:param name="max_ram" value="-1" value_type="e_integer" />
|
||||
<efx:param name="max_mult" value="-1" value_type="e_integer" />
|
||||
<efx:param name="min-sr-fanout" value="0" value_type="e_integer" />
|
||||
<efx:param name="min-ce-fanout" value="0" value_type="e_integer" />
|
||||
<efx:param name="mult-decomp-retime" value="0" value_type="e_option" />
|
||||
<efx:param name="mode" value="speed" value_type="e_option" />
|
||||
<efx:param name="operator-sharing" value="0" value_type="e_option" />
|
||||
<efx:param name="optimize-adder-tree" value="0" value_type="e_option" />
|
||||
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option" />
|
||||
<efx:param name="retiming" value="1" value_type="e_option" />
|
||||
<efx:param name="seq_opt" value="1" value_type="e_option" />
|
||||
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option" />
|
||||
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option" />
|
||||
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option" />
|
||||
<efx:param name="include" value="ip/sdram_controller" value_type="e_string" />
|
||||
<efx:param name="work_dir" value="work_syn" value_type="e_string"/>
|
||||
<efx:param name="write_efx_verilog" value="on" value_type="e_bool"/>
|
||||
<efx:param name="allow-const-ram-index" value="0" value_type="e_option"/>
|
||||
<efx:param name="blackbox-error" value="1" value_type="e_option"/>
|
||||
<efx:param name="blast_const_operand_adders" value="1" value_type="e_option"/>
|
||||
<efx:param name="bram_output_regs_packing" value="1" value_type="e_option"/>
|
||||
<efx:param name="create-onehot-fsms" value="0" value_type="e_option"/>
|
||||
<efx:param name="fanout-limit" value="0" value_type="e_integer"/>
|
||||
<efx:param name="hdl-compile-unit" value="1" value_type="e_option"/>
|
||||
<efx:param name="infer-clk-enable" value="3" value_type="e_option"/>
|
||||
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option"/>
|
||||
<efx:param name="max_ram" value="-1" value_type="e_integer"/>
|
||||
<efx:param name="max_mult" value="-1" value_type="e_integer"/>
|
||||
<efx:param name="min-sr-fanout" value="0" value_type="e_integer"/>
|
||||
<efx:param name="min-ce-fanout" value="0" value_type="e_integer"/>
|
||||
<efx:param name="mult-decomp-retime" value="0" value_type="e_option"/>
|
||||
<efx:param name="mode" value="speed" value_type="e_option"/>
|
||||
<efx:param name="operator-sharing" value="0" value_type="e_option"/>
|
||||
<efx:param name="optimize-adder-tree" value="0" value_type="e_option"/>
|
||||
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option"/>
|
||||
<efx:param name="retiming" value="1" value_type="e_option"/>
|
||||
<efx:param name="seq_opt" value="1" value_type="e_option"/>
|
||||
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option"/>
|
||||
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option"/>
|
||||
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option"/>
|
||||
<efx:param name="include" value="ip/sdram_controller" value_type="e_string"/>
|
||||
<efx:defmacro name="SDIO_AXI" value="1"/>
|
||||
<efx:defmacro name="EFINIX" value="1"/>
|
||||
</efx:synthesis>
|
||||
<efx:place_and_route tool_name="efx_pnr">
|
||||
<efx:param name="work_dir" value="work_pnr" value_type="e_string" />
|
||||
<efx:param name="verbose" value="off" value_type="e_bool" />
|
||||
<efx:param name="load_delaym" value="on" value_type="e_bool" />
|
||||
<efx:param name="optimization_level" value="TIMING_3" value_type="e_option" />
|
||||
<efx:param name="seed" value="1" value_type="e_integer" />
|
||||
<efx:param name="placer_effort_level" value="5" value_type="e_option" />
|
||||
<efx:param name="max_threads" value="-1" value_type="e_integer" />
|
||||
<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
|
||||
<efx:param name="verbose" value="off" value_type="e_bool"/>
|
||||
<efx:param name="load_delaym" value="on" value_type="e_bool"/>
|
||||
<efx:param name="optimization_level" value="TIMING_3" value_type="e_option"/>
|
||||
<efx:param name="seed" value="1" value_type="e_integer"/>
|
||||
<efx:param name="placer_effort_level" value="5" value_type="e_option"/>
|
||||
<efx:param name="max_threads" value="-1" value_type="e_integer"/>
|
||||
</efx:place_and_route>
|
||||
<efx:bitstream_generation tool_name="efx_pgm">
|
||||
<efx:param name="mode" value="active" value_type="e_option" />
|
||||
<efx:param name="width" value="1" value_type="e_option" />
|
||||
<efx:param name="enable_roms" value="smart" value_type="e_option" />
|
||||
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool" />
|
||||
<efx:param name="io_weak_pullup" value="on" value_type="e_bool" />
|
||||
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option" />
|
||||
<efx:param name="bitstream_compression" value="off" value_type="e_bool" />
|
||||
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool" />
|
||||
<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option" />
|
||||
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string" />
|
||||
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool" />
|
||||
<efx:param name="four_byte_addressing" value="off" value_type="e_bool" />
|
||||
<efx:param name="generate_bit" value="on" value_type="e_bool" />
|
||||
<efx:param name="generate_bitbin" value="off" value_type="e_bool" />
|
||||
<efx:param name="generate_hex" value="on" value_type="e_bool" />
|
||||
<efx:param name="generate_hexbin" value="off" value_type="e_bool" />
|
||||
<efx:param name="cold_boot" value="off" value_type="e_bool" />
|
||||
<efx:param name="cascade" value="off" value_type="e_option" />
|
||||
<efx:param name="mode" value="active" value_type="e_option"/>
|
||||
<efx:param name="width" value="1" value_type="e_option"/>
|
||||
<efx:param name="enable_roms" value="smart" value_type="e_option"/>
|
||||
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool"/>
|
||||
<efx:param name="io_weak_pullup" value="on" value_type="e_bool"/>
|
||||
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option"/>
|
||||
<efx:param name="bitstream_compression" value="off" value_type="e_bool"/>
|
||||
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool"/>
|
||||
<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option"/>
|
||||
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string"/>
|
||||
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool"/>
|
||||
<efx:param name="four_byte_addressing" value="off" value_type="e_bool"/>
|
||||
<efx:param name="generate_bit" value="on" value_type="e_bool"/>
|
||||
<efx:param name="generate_bitbin" value="off" value_type="e_bool"/>
|
||||
<efx:param name="generate_hex" value="on" value_type="e_bool"/>
|
||||
<efx:param name="generate_hexbin" value="off" value_type="e_bool"/>
|
||||
<efx:param name="cold_boot" value="off" value_type="e_bool"/>
|
||||
<efx:param name="cascade" value="off" value_type="e_option"/>
|
||||
</efx:bitstream_generation>
|
||||
<efx:debugger>
|
||||
<efx:param name="work_dir" value="work_dbg" value_type="e_string" />
|
||||
<efx:param name="auto_instantiation" value="off" value_type="e_bool" />
|
||||
<efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string" />
|
||||
<efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
|
||||
<efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
|
||||
<efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string"/>
|
||||
</efx:debugger>
|
||||
</efx:project>
|
||||
</efx:project>
|
||||
|
||||
Reference in New Issue
Block a user