change to asynchronous read

hw/efinix_fpga/leds.sv

@@ -9,19 +9,14 @@ module leds
     output logic [7:0] o_leds
 );
 
-logic re, we;
-assign re = rwb & cs;
-assign we = ~rwb & cs;
-
 logic [7:0] _data;
 
 assign o_leds = ~_data;
 
+assign o_data = _data;
+
 always @(negedge clk) begin
-    if (re) begin
-        o_data <= _data;
-    end 
-    else if (we) begin
+    if (~rwb & cs) begin
         _data <= i_data;
     end
 end