Change clk_2 to clk_cpu
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@@ -11,7 +11,7 @@ module super6502
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input button_reset,
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input pll_cpu_locked,
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input clk_50,
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input clk_2,
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input clk_cpu,
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input logic [15:0] cpu_addr,
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output logic [7:0] cpu_data_out,
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output logic [7:0] cpu_data_oe,
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@@ -56,11 +56,11 @@ assign cpu_nmib = '1;
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logic w_wait;
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assign cpu_rdy = ~w_wait;
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assign cpu_phi2 = clk_2;
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assign cpu_phi2 = clk_cpu;
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logic w_sdr_init_done;
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always @(posedge clk_2) begin
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always @(posedge clk_cpu) begin
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if (button_reset == '0) begin
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cpu_resb <= '0;
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end
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@@ -124,12 +124,12 @@ end
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rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom(
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.addr(cpu_addr[11:0]),
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.clk(clk_2),
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.clk(clk_cpu),
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.data(w_rom_data_out)
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);
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leds u_leds(
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.clk(clk_2),
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.clk(clk_cpu),
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.i_data(cpu_data_in),
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.o_data(w_leds_data_out),
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.cs(w_leds_cs),
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@@ -140,7 +140,7 @@ leds u_leds(
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logic w_timer_irqb;
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timer u_timer(
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.clk(clk_2),
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.clk(clk_cpu),
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.reset(~cpu_resb),
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.i_data(cpu_data_in),
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.o_data(w_timer_data_out),
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@@ -151,7 +151,7 @@ timer u_timer(
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);
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multiplier u_multiplier(
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.clk(clk_2),
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.clk(clk_cpu),
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.reset(~cpu_resb),
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.i_data(cpu_data_in),
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.o_data(w_multiplier_data_out),
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@@ -161,7 +161,7 @@ multiplier u_multiplier(
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);
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divider_wrapper u_divider(
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.clk(clk_2),
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.clk(clk_cpu),
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.divclk(clk_50),
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.reset(~cpu_resb),
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.i_data(cpu_data_in),
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@@ -174,7 +174,7 @@ divider_wrapper u_divider(
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logic w_uart_irqb;
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uart_wrapper u_uart(
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.clk(clk_2),
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.clk(clk_cpu),
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.clk_50(clk_50),
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.reset(~cpu_resb),
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.i_data(cpu_data_in),
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@@ -188,7 +188,7 @@ uart_wrapper u_uart(
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);
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spi_controller spi_controller(
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.i_clk(clk_2),
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.i_clk(clk_cpu),
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.i_rst(~cpu_resb),
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.i_cs(w_spi_cs),
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.i_rwb(cpu_rwb),
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@@ -204,7 +204,7 @@ spi_controller spi_controller(
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sdram_adapter u_sdram_adapter(
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.i_cpuclk(clk_2),
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.i_cpuclk(clk_cpu),
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.i_arst(~button_reset),
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.i_sysclk(i_sysclk),
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.i_sdrclk(i_sdrclk),
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@@ -234,7 +234,7 @@ sdram_adapter u_sdram_adapter(
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);
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interrupt_controller u_interrupt_controller(
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.clk(clk_2),
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.clk(clk_cpu),
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.reset(~cpu_resb),
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.i_data(cpu_data_in),
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.o_data(w_irq_data_out),
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