remote testing code

This commit is contained in:
Byron Lathi
2023-07-31 20:03:59 -07:00
parent 18b8ac7ccf
commit 6b42843f4b
2 changed files with 0 additions and 18 deletions

View File

@@ -1,13 +1,9 @@
CC=../cc65/bin/cl65
CFLAGS=-T -t none -I. --cpu "65C02"
test: CFLAGS=-T -t sim65c02 -I.
LDFLAGS=-C link.ld -m $(NAME).map
SIM=sim65
SIMARGS=-v -c -x 1000000
NAME=bootloader
TEST_BIN=test.bin
BIN=$(NAME).bin
HEX=$(NAME).hex
@@ -19,19 +15,8 @@ SRCS+=$(filter-out $(wildcard tests/*), $(wildcard **/*.s)) $(filter-out $(wildc
OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS)))
OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
TEST_SRCS=$(wildcard $(TESTS)/*.s) $(wildcard $(TESTS)/*.c)
TEST_OBJS+=$(patsubst %.s,%.o,$(filter %s,$(TEST_SRCS)))
TEST_OBJS+=$(patsubst %.c,%.o,$(filter %c,$(TEST_SRCS)))
TEST_OBJS+=$(filter-out boot.o,$(filter-out main.o,$(filter-out vectors.o,$(OBJS))))
all: $(HEX)
test: $(TEST_BIN)
$(SIM) $(SIMARGS) $(TEST_BIN)
$(TEST_BIN): $(OBJS) $(TEST_OBJS)
$(CC) $(CFLAGS) $(TEST_OBJS) -o $@
$(HEX): $(BIN)
objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX)
@@ -47,10 +32,8 @@ $(BIN): $(OBJS)
$(LISTS):
mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS))))
mkdir $(LISTS)/$(sort $(dir $(TEST_SRCS)))
.PHONY: clean
clean:
rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map
rm -rf $(TEST_OBJS) $(TEST_BIN)

View File

@@ -35,5 +35,4 @@ $(LISTS):
.PHONY: clean
clean:
rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map
rm -rf $(TEST_OBJS) $(TEST_BIN)