Add rtc code test

hw/efinix_fpga/simulation/Makefile

@@ -10,7 +10,7 @@ TEST_FOLDER?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)
 TEST_PROGRAM?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).hex
 
 STANDALONE_TB= interrupt_controller_tb mapper_tb rtc_tb
-CODE_TB= interrupt_controller_code_tb mapper_code_tb
+CODE_TB= interrupt_controller_code_tb mapper_code_tb rtc_code_tb
 
 #TODO implement something like sources.list
 

hw/efinix_fpga/simulation/tbs/rtc_code_tb.sv

@@ -0,0 +1,23 @@
+`timescale 1ns/1ps
+
+module rtc_code_tb();
+
+sim_top u_sim_top();
+
+always begin
+    if (
+        u_sim_top.w_cpu_addr == 16'h0 &&
+        u_sim_top.w_cpu_we == '1
+    ) begin
+        if (u_sim_top.w_cpu_data_from_cpu == 8'h6d) begin
+            $display("Good finish!");
+            $finish();
+        end else begin
+            $display("Bad finish!");
+            $finish_and_return(-1);
+        end
+    end
+    # 1;
+end
+
+endmodule

hw/efinix_fpga/src/super6502.sv

@@ -72,6 +72,8 @@ always @(posedge clk_cpu) begin
 end
 
 
+logic w_rtc_irq;
+
 logic w_mapper_cs;
 
 logic w_rom_cs;
@@ -83,6 +85,7 @@ logic w_divider_cs;
 logic w_uart_cs;
 logic w_spi_cs;
 logic w_irq_cs;
+logic w_rtc_cs;
 
 
 logic [7:0] w_rom_data_out;
@@ -93,6 +96,7 @@ logic [7:0] w_divider_data_out;
 logic [7:0] w_uart_data_out;
 logic [7:0] w_spi_data_out;
 logic [7:0] w_irq_data_out;
+logic [7:0] w_rtc_data_out;
 logic [7:0] w_sdram_data_out;
 
 logic [24:0] w_mapped_addr;
@@ -101,6 +105,7 @@ always_comb begin
     w_mapper_cs = cpu_addr >= 16'h200 && cpu_addr <= 16'h21f;
 
     w_rom_cs = w_mapped_addr >= 16'hf000 && w_mapped_addr <= 16'hffff;
+    w_rtc_cs = w_mapped_addr >= 16'heffe && w_mapped_addr <= 16'hefff;
     w_irq_cs = w_mapped_addr >= 16'heffc && w_mapped_addr <= 16'heffd;
     w_timer_cs = w_mapped_addr >= 16'heff8 && w_mapped_addr <= 16'heffb;
     w_multiplier_cs = w_mapped_addr >= 16'heff0 && w_mapped_addr <= 16'heff7;
@@ -117,7 +122,8 @@ always_comb begin
         w_uart_cs | 
         w_spi_cs |
         w_leds_cs |
-        w_irq_cs 
+        w_irq_cs |
+        w_rtc_cs
     );
 
 
@@ -139,6 +145,8 @@ always_comb begin
         cpu_data_out = w_spi_data_out;
     else if (w_irq_cs)
         cpu_data_out = w_irq_data_out;
+    else if (w_rtc_cs)
+        cpu_data_out = w_rtc_cs;
     else if (w_sdram_cs)
         cpu_data_out = w_sdram_data_out;
     else
@@ -269,7 +277,9 @@ sdram_adapter u_sdram_adapter(
 
 logic w_irq;
 assign cpu_irqb = ~w_irq;
-logic [255:0] int_in;
+logic [255:0] w_int_in;
+
+assign w_int_in[255:1] = 0;
 
 interrupt_controller u_interrupt_controller(
     .clk(clk_cpu),
@@ -283,5 +293,17 @@ interrupt_controller u_interrupt_controller(
     .int_out(w_irq)
 );
 
+rtc u_rtc(
+    .clk(clk_cpu),
+    .reset(~cpu_resb),
+    .rwb(cpu_rwb),
+    .cs(w_rtc_cs),
+    .addr(w_mapped_addr[0]),
+    .i_data(cpu_data_in),
+    .o_data(w_rtc_data_out),
+    .irq(w_rtc_irq)
+);
+
+assign w_int_in[0] = w_rtc_irq;
 
 endmodule