Merge branch '50-full-chip-sims-should-be-optional-and-have-better-finish-conditions' into 'master'

Resolve "Full chip sims should be optional and have better finish conditions."

Closes #50

See merge request bslathi19/super6502!44

.gitlab-ci.yml

@@ -47,22 +47,6 @@ build fpga:       # This job runs in the build stage, which runs first.
     - cd hw/efinix_fpga
     - make
 
-build sim:
-  tags:
-   - iverilog
-   - linux
-  stage: build
-  artifacts:
-    paths:
-      - hw/efinix_fpga/simulation/sim_top
-      - hw/efinix_fpga/simulation/init_hex.mem
-  script:  
-    - source init_env.sh
-    - cd hw/efinix_fpga/simulation
-    - make sim_top
-  dependencies:
-    - build toolchain
-
 build bios:
   tags:
     - linux
@@ -85,22 +69,9 @@ build kernel:
   dependencies:
     - build toolchain
 
-run sim:
-  tags:
-    - linux
-    - iverilog
-  stage: simulate
-  artifacts:
-    paths:
-      - hw/efinix_fpga/simulation/sim_top.vcd
-  script:
-    - source init_env.sh
-    - cd hw/efinix_fpga/simulation
-    - make sim
-  dependencies:
-    - build toolchain
 
 full sim:
+  when: manual
   tags:
     - linux
     - iverilog

hw/efinix_fpga/simulation/src/sim_top.sv

@@ -53,7 +53,7 @@ initial begin
     button_reset <= '0;
     repeat(10) @(r_clk_cpu);
     button_reset <= '1;
-    repeat(1250000) @(posedge r_clk_cpu);
+    repeat(1500000) @(posedge r_clk_cpu);
     $finish();
 end