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Remove fpga RAM

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This removes the ram from inside the FPGA. All RAM is now located in the
external SDRAM instead.

The ROM is still in the FPGA to allow easier programming.
This commit is contained in:
Byron Lathi
2022-03-21 14:01:16 -05:00
parent c97f2d807a
commit 74210f57f7
6 changed files with 4 additions and 202 deletions
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10
hw/fpga/hvl/cs_testbench.sv
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@@ -5,7 +5,6 @@ timeunit 10ns;
timeprecision 1ns;
logic [15:0] addr;
logic ram_cs;
logic sdram_cs;
logic rom_cs;
logic hex_cs;
@@ -13,7 +12,7 @@ logic board_io_cs;
logic uart_cs;
logic irq_cs;
int cs_count = ram_cs + sdram_cs + rom_cs + hex_cs + uart_cs + board_io_cs;
int cs_count = sdram_cs + rom_cs + hex_cs + uart_cs + board_io_cs;
addr_decode dut(.*);
@@ -25,12 +24,7 @@ initial begin : TEST_VECTORS
assert(cs_count < 2)
else
$error("Multiple chip selects present!");
if (i < 16'h4000) begin
assert(ram_cs == '1)
else
$error("Bad CS! addr=%4x should have ram_cs!", addr);
end
if (i >= 16'h4000 && i < 16'h7ff0) begin
if (i < 16'h7ff0) begin
assert(sdram_cs == '1)
else
$error("Bad CS! addr=%4x should have sdram_cs!", addr);