bslathi19/super6502
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Remove fpga RAM

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This removes the ram from inside the FPGA. All RAM is now located in the
external SDRAM instead.

The ROM is still in the FPGA to allow easier programming.
This commit is contained in:
Byron Lathi
2022-03-21 14:01:16 -05:00
parent c97f2d807a
commit 74210f57f7
6 changed files with 4 additions and 202 deletions
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15
hw/fpga/super6502.sv
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@@ -56,13 +56,11 @@ assign cpu_data = cpu_rwb ? cpu_data_out : 'z;
logic [7:0] rom_data_out;
logic [7:0] ram_data_out;
logic [7:0] sdram_data_out;
logic [7:0] uart_data_out;
logic [7:0] irq_data_out;
logic [7:0] board_io_data_out;
logic ram_cs;
logic sdram_cs;
logic rom_cs;
logic hex_cs;
@@ -88,7 +86,6 @@ assign cpu_irqb = irq_data_out == 0;
addr_decode decode(
.addr(cpu_addr),
.ram_cs(ram_cs),
.sdram_cs(sdram_cs),
.rom_cs(rom_cs),
.hex_cs(hex_cs),
@@ -99,9 +96,7 @@ addr_decode decode(
always_comb begin
if (ram_cs)
cpu_data_out = ram_data_out;
else if (sdram_cs)
if (sdram_cs)
cpu_data_out = sdram_data_out;
else if (rom_cs)
cpu_data_out = rom_data_out;
@@ -140,14 +135,6 @@ sdram sdram(
.DRAM_WE_N(DRAM_WE_N) //.we_n
);
ram main_memory(
.address(cpu_addr[14:0]),
.clock(clk),
.data(cpu_data_in),
.wren(~cpu_rwb & ram_cs),
.q(ram_data_out)
);
rom boot_rom(
.address(cpu_addr[14:0]),