Create UART and uart_wrapper

hw/efinix_fpga/ip/uart/uart_tmpl.vhd

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+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+------------- Begin Cut here for COMPONENT Declaration ------
+COMPONENT uart is
+PORT (
+tx_o : out std_logic;
+rx_i : in std_logic;
+tx_busy : out std_logic;
+rx_data : out std_logic_vector(7 downto 0);
+rx_data_valid : out std_logic;
+rx_error : out std_logic;
+rx_parity_error : out std_logic;
+rx_busy : out std_logic;
+baud_x16_ce : out std_logic;
+clk : in std_logic;
+reset : in std_logic;
+tx_data : in std_logic_vector(7 downto 0);
+baud_rate : in std_logic_vector(2 downto 0);
+tx_en : in std_logic);
+END COMPONENT;
+---------------------- End COMPONENT Declaration ------------
+
+------------- Begin Cut here for INSTANTIATION Template -----
+u_uart : uart
+PORT MAP (
+tx_o => tx_o,
+rx_i => rx_i,
+tx_busy => tx_busy,
+rx_data => rx_data,
+rx_data_valid => rx_data_valid,
+rx_error => rx_error,
+rx_parity_error => rx_parity_error,
+rx_busy => rx_busy,
+baud_x16_ce => baud_x16_ce,
+clk => clk,
+reset => reset,
+tx_data => tx_data,
+baud_rate => baud_rate,
+tx_en => tx_en);
+------------------------ End INSTANTIATION Template ---------