Create UART and uart_wrapper

hw/efinix_fpga/addr_decode.sv

@@ -7,6 +7,7 @@ module addr_decode
     output o_timer_cs,
     output o_multiplier_cs,
     output o_divider_cs,
+    output o_uart_cs,
     output o_sdram_cs
 );
 
@@ -14,6 +15,7 @@ assign o_rom_cs = i_addr >= 16'hf000 && i_addr <= 16'hffff;
 assign o_timer_cs = i_addr >= 16'heff8 && i_addr <= 16'heffb;
 assign o_multiplier_cs = i_addr >= 16'heff0 && i_addr <= 16'heff7;
 assign o_divider_cs = i_addr >= 16'hefe7 && i_addr <= 16'hefef;
+assign o_uart_cs = i_addr >= 16'hefe5 && i_addr <= 16'hefe6;
 assign o_leds_cs = i_addr == 16'hefff;
 assign o_sdram_cs = i_addr < 16'h8000;
 

hw/efinix_fpga/ip/uart/settings.json

@@ -0,0 +1,34 @@
+{
+    "args": [
+        "-o",
+        "uart",
+        "--base_path",
+        "/home/byron/Projects/super6502/hw/efinix_fpga/ip",
+        "--vlnv",
+        {
+            "vendor": "efinixinc.com",
+            "library": "serial_interface",
+            "name": "efx_uart",
+            "version": "2.0"
+        }
+    ],
+    "conf": {
+        "BYTE": "1",
+        "CLOCK_FREQ": "50000000",
+        "BAUD": "115200",
+        "ENABLE_PARITY": "0",
+        "FIX_BAUDRATE": "1",
+        "PARITY_MODE": "0",
+        "BOOTUP_CHECK": "0"
+    },
+    "output": {
+        "external_source_source": [
+            "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart.v",
+            "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_define.vh",
+            "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_tmpl.vhd",
+            "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_tmpl.v"
+        ]
+    },
+    "sw_version": "2022.2.322",
+    "generated_date": "2023-01-12T01:01:22.177819"
+}

hw/efinix_fpga/ip/uart/uart_define.vh

@@ -0,0 +1,52 @@
+// =============================================================================
+// Generated by efx_ipmgr
+// Version: 2022.2.322
+// IP Version: 2.0
+// =============================================================================
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+
+localparam BYTE = 1;
+localparam CLOCK_FREQ = 50000000;
+localparam BAUD = 115200;
+localparam ENABLE_PARITY = 0;
+localparam FIX_BAUDRATE = 1;
+localparam PARITY_MODE = 0;
+localparam BOOTUP_CHECK = 0;

hw/efinix_fpga/ip/uart/uart_tmpl.v

@@ -0,0 +1,55 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+
+uart u_uart(
+.tx_o ( tx_o ),
+.rx_i ( rx_i ),
+.tx_busy ( tx_busy ),
+.rx_data ( rx_data ),
+.rx_data_valid ( rx_data_valid ),
+.rx_error ( rx_error ),
+.rx_parity_error ( rx_parity_error ),
+.rx_busy ( rx_busy ),
+.baud_x16_ce ( baud_x16_ce ),
+.clk ( clk ),
+.reset ( reset ),
+.tx_data ( tx_data ),
+.baud_rate ( baud_rate ),
+.tx_en ( tx_en )
+);

hw/efinix_fpga/ip/uart/uart_tmpl.vhd

@@ -0,0 +1,76 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+------------- Begin Cut here for COMPONENT Declaration ------
+COMPONENT uart is
+PORT (
+tx_o : out std_logic;
+rx_i : in std_logic;
+tx_busy : out std_logic;
+rx_data : out std_logic_vector(7 downto 0);
+rx_data_valid : out std_logic;
+rx_error : out std_logic;
+rx_parity_error : out std_logic;
+rx_busy : out std_logic;
+baud_x16_ce : out std_logic;
+clk : in std_logic;
+reset : in std_logic;
+tx_data : in std_logic_vector(7 downto 0);
+baud_rate : in std_logic_vector(2 downto 0);
+tx_en : in std_logic);
+END COMPONENT;
+---------------------- End COMPONENT Declaration ------------
+
+------------- Begin Cut here for INSTANTIATION Template -----
+u_uart : uart
+PORT MAP (
+tx_o => tx_o,
+rx_i => rx_i,
+tx_busy => tx_busy,
+rx_data => rx_data,
+rx_data_valid => rx_data_valid,
+rx_error => rx_error,
+rx_parity_error => rx_parity_error,
+rx_busy => rx_busy,
+baud_x16_ce => baud_x16_ce,
+clk => clk,
+reset => reset,
+tx_data => tx_data,
+baud_rate => baud_rate,
+tx_en => tx_en);
+------------------------ End INSTANTIATION Template ---------

hw/efinix_fpga/super6502.peri.xml

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2022.1.226" db_version="20221999" last_change_date="Thu Dec 22 20:19:31 2022" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
+<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2022.2.322" db_version="20222999" last_change_date="Wed Jan 11 20:59:16 2023" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
     <efxpt:device_info>
         <efxpt:iobank_info>
             <efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
@@ -306,6 +306,28 @@
         <efxpt:gpio name="pll_in" gpio_def="GPIOR_157" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
             <efxpt:input_config name="pll_in" name_ddio_lo="" conn_type="pll_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
         </efxpt:gpio>
+        <efxpt:gpio name="sd_clk" gpio_def="GPIOL_26" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="sd_clk" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="sd_cmd" gpio_def="GPIOL_25" mode="inout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="i_sd_cmd" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="o_sd_cmd" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
+            <efxpt:output_enable_config name="sd_cmd_OE" is_register="false" clock_name="" is_clock_inverted="false"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="sd_cs" gpio_def="GPIOL_36" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="sd_cs" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="sd_data" gpio_def="GPIOL_29" mode="inout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="i_sd_data" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="o_sd_data" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
+            <efxpt:output_enable_config name="sd_data_OE" is_register="false" clock_name="" is_clock_inverted="false"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="uart_rx" gpio_def="GPIOL_11" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="uart_rx" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="uart_tx" gpio_def="GPIOL_12" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="uart_tx" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
+        </efxpt:gpio>
         <efxpt:global_unused_config state="input with weak pullup"/>
         <efxpt:bus name="cpu_data" mode="inout" msb="7" lsb="0"/>
         <efxpt:bus name="cpu_addr" mode="input" msb="15" lsb="0"/>

hw/efinix_fpga/super6502.sv

@@ -35,7 +35,10 @@ module super6502
     input	logic [15:0] i_sdr_DATA,
     output	logic [15:0] o_sdr_DATA,
     output	logic [15:0] o_sdr_DATA_oe,
-    output	logic [1:0] o_sdr_DQM
+    output	logic [1:0] o_sdr_DQM,
+
+    input uart_rx,
+    output uart_tx
 
 );
 
@@ -68,6 +71,7 @@ logic w_sdram_cs;
 logic w_timer_cs;
 logic w_multiplier_cs;
 logic w_divider_cs;
+logic w_uart_cs;
 
 addr_decode u_addr_decode(
     .i_addr(cpu_addr),
@@ -76,6 +80,7 @@ addr_decode u_addr_decode(
     .o_timer_cs(w_timer_cs),
     .o_multiplier_cs(w_multiplier_cs),
     .o_divider_cs(w_divider_cs),
+    .o_uart_cs(w_uart_cs),
     .o_sdram_cs(w_sdram_cs)
 );
 
@@ -84,6 +89,7 @@ logic [7:0] w_leds_data_out;
 logic [7:0] w_timer_data_out;
 logic [7:0] w_multiplier_data_out;
 logic [7:0] w_divider_data_out;
+logic [7:0] w_uart_data_out;
 logic [7:0] w_sdram_data_out;
 
 always_comb begin
@@ -97,6 +103,8 @@ always_comb begin
         cpu_data_out = w_multiplier_data_out;
     else if (w_divider_cs)
         cpu_data_out = w_divider_data_out;
+    else if (w_uart_cs)
+        cpu_data_out = w_uart_data_out;
     else if (w_sdram_cs)
         cpu_data_out = w_sdram_data_out;
     else
@@ -158,6 +166,22 @@ divider_wrapper u_divider(
     .addr(cpu_addr[2:0])
 );
 
+logic w_uart_irqb;
+
+uart_wrapper u_uart(
+    .clk(clk_2),
+    .clk_50(clk_50),
+    .reset(~cpu_resb),
+    .i_data(cpu_data_in),
+    .o_data(w_uart_data_out),
+    .cs(w_uart_cs),
+    .rwb(cpu_rwb),
+    .addr(cpu_addr[0]),
+    .rx_i(uart_rx),
+    .tx_o(uart_tx),
+    .irqb(w_uart_irqb)
+);
+
 sdram_adapter u_sdram_adapter(
     .i_cpuclk(clk_2),
     .i_arst(~button_reset),

hw/efinix_fpga/super6502.xml

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<efx:project name="super6502" description="" last_change_date="Thu January 5 2023 19:19:10" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project name="super6502" description="" last_change_date="Wed January 11 2023 21:04:23" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion"/>
         <efx:device name="T20F256"/>
@@ -20,6 +20,7 @@
         <efx:design_file name="interrupt_controller.sv" version="default" library="default"/>
         <efx:design_file name="multiplier.sv" version="default" library="default"/>
         <efx:design_file name="divider_wrapper.sv" version="default" library="default"/>
+        <efx:design_file name="uart_wrapper.sv" version="default" library="default"/>
         <efx:top_vhdl_arch name=""/>
     </efx:design_info>
     <efx:constraint_info>
@@ -35,6 +36,9 @@
         <efx:ip instance_name="divider" path="ip/divider/settings.json">
             <efx:ip_src_file name="divider.v"/>
         </efx:ip>
+        <efx:ip instance_name="uart" path="ip/uart/settings.json">
+            <efx:ip_src_file name="uart.v"/>
+        </efx:ip>
     </efx:ip_info>
     <efx:synthesis tool_name="efx_map">
         <efx:param name="work_dir" value="work_syn" value_type="e_string"/>
@@ -62,6 +66,7 @@
         <efx:param name="min-ce-fanout" value="0" value_type="e_integer"/>
         <efx:param name="include" value="ip/sdram_controller" value_type="e_string"/>
         <efx:param name="include" value="ip/divider" value_type="e_string"/>
+        <efx:param name="include" value="ip/uart" value_type="e_string"/>
     </efx:synthesis>
     <efx:place_and_route tool_name="efx_pnr">
         <efx:param name="work_dir" value="work_pnr" value_type="e_string"/>

hw/efinix_fpga/uart_wrapper.sv

@@ -0,0 +1,106 @@
+module uart_wrapper(
+    input clk,
+    input clk_50,
+    input reset,
+    input [7:0] i_data,
+    output logic [7:0] o_data,
+    input cs,
+    input rwb,
+    input addr,
+
+    input rx_i,
+    output tx_o,
+
+    output logic irqb
+);
+
+logic status, control;
+
+logic tx_busy, rx_busy;
+
+logic rx_data_valid, rx_error, rx_parity_error;
+logic baud_x16_ce;
+
+logic tx_en;
+
+logic [7:0] tx_data, rx_data;
+
+uart u_uart(
+    .tx_o ( tx_o ),
+    .rx_i ( rx_i ),
+    .tx_busy ( tx_busy ),
+    .rx_data ( rx_data ),
+    .rx_data_valid ( rx_data_valid ),
+    .rx_error ( rx_error ),
+    .rx_parity_error ( rx_parity_error ),
+    .rx_busy ( rx_busy ),
+    .baud_x16_ce ( baud_x16_ce ),
+    .clk ( clk_50 ),
+    .reset ( reset ),
+    .tx_data ( tx_data ),
+    .baud_rate ( baud_rate ),
+    .tx_en ( tx_en )
+);
+
+enum bit [1:0] {READY, WAIT, TRANSMIT} state, next_state;
+
+always_ff @(negedge clk) begin
+    if (reset) begin
+        state = READY;
+        irqb <= '1;
+    end else begin
+        state <= next_state;
+    end
+
+    case (addr)
+        1'b0: begin
+            tx_data <= i_data;
+        end 
+
+        1'b1: begin
+            control <= i_data;
+        end
+    endcase
+
+end
+
+always_comb begin
+    case (addr)
+        1'b0: begin
+            o_data = rx_data;
+        end 
+
+        1'b1: begin
+            o_data = status;
+        end
+    endcase
+end
+
+always_comb begin
+    next_state = state;
+
+    tx_en = 1'b0;
+
+    case (state)
+        READY: begin
+            if (~rwb && addr == 1'b0) begin //write to transmit
+                tx_en = 1'b1;
+                next_state = WAIT;
+            end
+        end
+
+        WAIT: begin
+            if (tx_busy) begin
+                next_state = TRANSMIT;
+            end
+        end
+
+        TRANSMIT: begin
+            if (~tx_busy) begin
+                next_state = READY;
+            end
+        end
+    endcase
+end
+
+endmodule