Change divider to pipelined version

The pipelining allows the cpu to run at a faster clock speed but results
in latency. At the current 2 MHz, there is 1 cycle of latency which is
negligible because the 6502 cannot do sequential data memory accesses.

In the future, there will have to be some sort of status flag or
interrupt showing that the divider is ready.

hw/efinix_fpga/divider_wrapper.sv

@@ -1,5 +1,6 @@
 module divider_wrapper(
     input clk,
+    input divclk,
     input reset,
     input [7:0] i_data,
     output logic [7:0] o_data,
@@ -11,6 +12,8 @@ module divider_wrapper(
 logic [15:0] numer, denom;
 logic [15:0] quotient, remain;
 
+logic [15:0] r_quotient, r_remain;
+
 logic clken, rfd;
 
 assign clken = '1;
@@ -20,7 +23,7 @@ divider u_divider(
 .numer ( numer ),
 .denom ( denom ),
 .clken ( clken ),
-.clk ( clk ),
+.clk ( divclk ),
 .reset ( reset ),
 .quotient ( quotient ),
 .remain ( remain ),
@@ -56,23 +59,30 @@ always_ff @(negedge clk) begin
     end
 end
 
+always_ff @(posedge divclk) begin
+    if (rfd) begin
+        r_quotient <= quotient;
+        r_remain <= remain;
+    end
+end
+
 always_comb begin
 
     case (addr)
         3'h4: begin
-            o_data = quotient[7:0];
+            o_data = r_quotient[7:0];
         end
 
         3'h5: begin
-            o_data = quotient[15:8];
+            o_data = r_quotient[15:8];
         end
 
         3'h6: begin
-            o_data = remain[7:0];
+            o_data = r_remain[7:0];
         end
 
         3'h7: begin
-            o_data = remain[15:8];
+            o_data = r_remain[15:8];
         end
 
     endcase