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Move to 4 TCP units for synthesis

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Otherwise it does not fit in the T20
This commit is contained in:
Byron Lathi
2024-09-09 22:59:59 -07:00
parent 4612acbc4a
commit 8be97b45ae
8 changed files with 52 additions and 52 deletions
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6
hw/super6502_fpga/src/sub/network_processor/src/regs/ntw_top_regfile.sv
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@@ -262,8 +262,8 @@ module ntw_top_regfile (
is_external = '0;
decoded_reg_strb.mac = cpuif_req_masked & (cpuif_addr >= 10'h0) & (cpuif_addr <= 10'h0 + 10'h7);
is_external |= cpuif_req_masked & (cpuif_addr >= 10'h0) & (cpuif_addr <= 10'h0 + 10'h7);
decoded_reg_strb.tcp_top = cpuif_req_masked & (cpuif_addr >= 10'h200) & (cpuif_addr <= 10'h200 + 10'h1ff);
is_external |= cpuif_req_masked & (cpuif_addr >= 10'h200) & (cpuif_addr <= 10'h200 + 10'h1ff);
decoded_reg_strb.tcp_top = cpuif_req_masked & (cpuif_addr >= 10'h200) & (cpuif_addr <= 10'h200 + 10'hff);
is_external |= cpuif_req_masked & (cpuif_addr >= 10'h200) & (cpuif_addr <= 10'h200 + 10'hff);
decoded_strb_is_external = is_external;
external_req = is_external;
end
@@ -289,7 +289,7 @@ module ntw_top_regfile (
assign hwif_out.mac.wr_data = decoded_wr_data;
assign hwif_out.mac.wr_biten = decoded_wr_biten;
assign hwif_out.tcp_top.req = decoded_reg_strb.tcp_top;
assign hwif_out.tcp_top.addr = decoded_addr[9:0];
assign hwif_out.tcp_top.addr = decoded_addr[8:0];
assign hwif_out.tcp_top.req_is_wr = decoded_req_is_wr;
assign hwif_out.tcp_top.wr_data = decoded_wr_data;
assign hwif_out.tcp_top.wr_biten = decoded_wr_biten;

2
hw/super6502_fpga/src/sub/network_processor/src/regs/ntw_top_regfile_pkg.sv
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@@ -33,7 +33,7 @@ package ntw_top_regfile_pkg;
typedef struct {
logic req;
logic [8:0] addr;
logic [7:0] addr;
logic req_is_wr;
logic [31:0] wr_data;
logic [31:0] wr_biten;

26
hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_top_regfile.sv
View File

@@ -7,7 +7,7 @@ module tcp_top_regfile (
input wire s_cpuif_req,
input wire s_cpuif_req_is_wr,
input wire [8:0] s_cpuif_addr,
input wire [7:0] s_cpuif_addr,
input wire [31:0] s_cpuif_wr_data,
input wire [31:0] s_cpuif_wr_biten,
output wire s_cpuif_req_stall_wr,
@@ -27,7 +27,7 @@ module tcp_top_regfile (
//--------------------------------------------------------------------------
logic cpuif_req;
logic cpuif_req_is_wr;
logic [8:0] cpuif_addr;
logic [7:0] cpuif_addr;
logic [31:0] cpuif_wr_data;
logic [31:0] cpuif_wr_biten;
logic cpuif_req_stall_wr;
@@ -83,12 +83,12 @@ module tcp_top_regfile (
// Address Decode
//--------------------------------------------------------------------------
typedef struct {
logic tcp_streams[8];
logic tcp_streams[4];
} decoded_reg_strb_t;
decoded_reg_strb_t decoded_reg_strb;
logic decoded_strb_is_external;
logic [8:0] decoded_addr;
logic [7:0] decoded_addr;
logic decoded_req;
logic decoded_req_is_wr;
@@ -98,9 +98,9 @@ module tcp_top_regfile (
always_comb begin
automatic logic is_external;
is_external = '0;
for(int i0=0; i0<8; i0++) begin
decoded_reg_strb.tcp_streams[i0] = cpuif_req_masked & (cpuif_addr >= 9'h0 + i0*9'h40) & (cpuif_addr <= 9'h0 + i0*9'h40 + 9'h2f);
is_external |= cpuif_req_masked & (cpuif_addr >= 9'h0 + i0*9'h40) & (cpuif_addr <= 9'h0 + i0*9'h40 + 9'h2f);
for(int i0=0; i0<4; i0++) begin
decoded_reg_strb.tcp_streams[i0] = cpuif_req_masked & (cpuif_addr >= 8'h0 + i0*8'h40) & (cpuif_addr <= 8'h0 + i0*8'h40 + 8'h2f);
is_external |= cpuif_req_masked & (cpuif_addr >= 8'h0 + i0*8'h40) & (cpuif_addr <= 8'h0 + i0*8'h40 + 8'h2f);
end
decoded_strb_is_external = is_external;
external_req = is_external;
@@ -121,7 +121,7 @@ module tcp_top_regfile (
for(genvar i0=0; i0<8; i0++) begin
for(genvar i0=0; i0<4; i0++) begin
assign hwif_out.tcp_streams[i0].req = decoded_reg_strb.tcp_streams[i0];
assign hwif_out.tcp_streams[i0].addr = decoded_addr[5:0];
assign hwif_out.tcp_streams[i0].req_is_wr = decoded_req_is_wr;
@@ -135,7 +135,7 @@ module tcp_top_regfile (
always_comb begin
automatic logic wr_ack;
wr_ack = '0;
for(int i0=0; i0<8; i0++) begin
for(int i0=0; i0<4; i0++) begin
wr_ack |= hwif_in.tcp_streams[i0].wr_ack;
end
external_wr_ack = wr_ack;
@@ -151,7 +151,7 @@ module tcp_top_regfile (
always_comb begin
automatic logic rd_ack;
rd_ack = '0;
for(int i0=0; i0<8; i0++) begin
for(int i0=0; i0<4; i0++) begin
rd_ack |= hwif_in.tcp_streams[i0].rd_ack;
end
readback_external_rd_ack_c = rd_ack;
@@ -166,8 +166,8 @@ module tcp_top_regfile (
logic [31:0] readback_data;
// Assign readback values to a flattened array
logic [31:0] readback_array[8];
for(genvar i0=0; i0<8; i0++) begin
logic [31:0] readback_array[4];
for(genvar i0=0; i0<4; i0++) begin
assign readback_array[i0*1 + 0] = hwif_in.tcp_streams[i0].rd_ack ? hwif_in.tcp_streams[i0].rd_data : '0;
end
@@ -177,7 +177,7 @@ module tcp_top_regfile (
readback_done = decoded_req & ~decoded_req_is_wr & ~decoded_strb_is_external;
readback_err = '0;
readback_data_var = '0;
for(int i=0; i<8; i++) readback_data_var |= readback_array[i];
for(int i=0; i<4; i++) readback_data_var |= readback_array[i];
readback_data = readback_data_var;
end

6
hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_top_regfile_pkg.sv
View File

@@ -4,7 +4,7 @@
package tcp_top_regfile_pkg;
localparam TCP_TOP_REGFILE_DATA_WIDTH = 32;
localparam TCP_TOP_REGFILE_MIN_ADDR_WIDTH = 9;
localparam TCP_TOP_REGFILE_MIN_ADDR_WIDTH = 8;
typedef struct {
logic rd_ack;
@@ -13,7 +13,7 @@ package tcp_top_regfile_pkg;
} tcp_stream_regs__external__in_t;
typedef struct {
tcp_stream_regs__external__in_t tcp_streams[8];
tcp_stream_regs__external__in_t tcp_streams[4];
} tcp_top_regfile__in_t;
typedef struct {
@@ -25,6 +25,6 @@ package tcp_top_regfile_pkg;
} tcp_stream_regs__external__out_t;
typedef struct {
tcp_stream_regs__external__out_t tcp_streams[8];
tcp_stream_regs__external__out_t tcp_streams[4];
} tcp_top_regfile__out_t;
endpackage

2
hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_top_regs.rdl
View File

@@ -1,3 +1,3 @@
addrmap tcp_top_regfile{
external tcp_stream_regs tcp_streams[8] += 0x40;
external tcp_stream_regs tcp_streams[4] += 0x40;
};

22
hw/super6502_fpga/src/sub/network_processor/src/tcp.sv
View File

@@ -124,17 +124,17 @@ axilxbar #(
.S_AXI_RDATA ({xbar_s_m2s_axi_rdata, xbar_s_s2m_axi_rdata }),
.S_AXI_RRESP ({xbar_s_m2s_axi_rresp, xbar_s_s2m_axi_rresp }),
.M_AXI_AWADDR (),
.M_AXI_AWPROT (),
.M_AXI_AWVALID (),
.M_AXI_AWREADY ('0),
.M_AXI_WDATA (),
.M_AXI_WSTRB (),
.M_AXI_WVALID (),
.M_AXI_WREADY ('0),
.M_AXI_BRESP ('0),
.M_AXI_BVALID ('0),
.M_AXI_BREADY (),
.M_AXI_AWADDR (m_dma_axil.awaddr),
.M_AXI_AWPROT (m_dma_axil.awprot),
.M_AXI_AWVALID (m_dma_axil.awvalid),
.M_AXI_AWREADY (m_dma_axil.awready),
.M_AXI_WDATA (m_dma_axil.wdata),
.M_AXI_WSTRB (m_dma_axil.wstrb),
.M_AXI_WVALID (m_dma_axil.wvalid),
.M_AXI_WREADY (m_dma_axil.wready),
.M_AXI_BRESP (m_dma_axil.bresp),
.M_AXI_BVALID (m_dma_axil.bvalid),
.M_AXI_BREADY (m_dma_axil.bready),
.M_AXI_ARADDR (m_dma_axil.araddr),
.M_AXI_ARPROT (m_dma_axil.arprot),