Add timer and test program

hw/efinix_fpga/addr_decode.sv

@@ -4,11 +4,13 @@ module addr_decode
 
     output o_rom_cs,
     output o_leds_cs,
+    output o_timer_cs,
     output o_sdram_cs
 );
 
 assign o_rom_cs = i_addr >= 16'hf000 && i_addr <= 16'hffff;
 assign o_leds_cs = i_addr == 16'hefff;
+assign o_timer_cs = i_addr >= 16'heff8 && i_addr <= 16'heffe;
 assign o_sdram_cs = i_addr < 16'h8000;
 
 endmodule

hw/efinix_fpga/ip/bram/bram_ini.vh

@@ -4,9 +4,9 @@ input integer index;//Mode type
 input integer val_; //Port A index, Port B Index, Number of Items in Loop, Port A Start, Port B Start, reserved 
 case (index)
    0: bram_ini_table=
-(val_== 0)?256'h000000020000f700010000ca00010000000009d000ff00010000bd0000a000a2:
+(val_== 0)?256'h00ef000ff0009c0001000085000ef000f8000ad000ef000fd0008d000ff000a9:
-(val_== 1)?256'h060000ef000ff0008d0006800000000a90004800055000a9000fe00080000100:
+(val_== 1)?256'h086000f40009000020000e90003800010000e500038000aa000ef000f8000ad0:
-(val_== 2)?256'h0000000000000000000000000000000000000000000000000000000000000000:
+(val_== 2)?256'h00000000000000000000000000000000000ed00080000ef000ff000ee0001000:
 (val_== 3)?256'h0000000000000000000000000000000000000000000000000000000000000000:
 (val_== 4)?256'h0000000000000000000000000000000000000000000000000000000000000000:
 (val_== 5)?256'h0000000000000000000000000000000000000000000000000000000000000000:

hw/efinix_fpga/ip/bram/init_hex.mem

@@ -1,35 +1,35 @@
-a2
+a9
-0a
-bd
-10
 ff
-9d
-00
-10
-ca
-10
-f7
-20
-00
-10
-80
-fe
-a9
-55
-48
-a9
-00
-68
 8d
+fd
+ef
+ad
+f8
+ef
+85
+10
+9c
 ff
 ef
-60
+ad
-00
+f8
-00
+ef
-00
+aa
-00
+38
-00
+e5
-00
+10
+38
+e9
+20
+90
+f4
+86
+10
+ee
+ff
+ef
+80
+ed
 00
 00
 00

hw/efinix_fpga/super6502.sv

@@ -66,23 +66,28 @@ end
 logic w_rom_cs;
 logic w_leds_cs;
 logic w_sdram_cs;
+logic w_timer_cs;
 
 addr_decode u_addr_decode(
     .i_addr(cpu_addr),
     .o_rom_cs(w_rom_cs),
     .o_leds_cs(w_leds_cs),
+    .o_timer_cs(w_timer_cs),
     .o_sdram_cs(w_sdram_cs)
 );
 
 logic [7:0] w_rom_data_out;
 logic [7:0] w_leds_data_out;
+logic [7:0] w_timer_data_out;
 logic [7:0] w_sdram_data_out;
 
 always_comb begin
     if (w_rom_cs)
         cpu_data_out = w_rom_data_out;
     else if (w_leds_cs)
-        cpu_data_out =  w_leds_data_out;
+        cpu_data_out = w_leds_data_out;
+    else if (w_timer_cs)
+        cpu_data_out = w_timer_data_out;
     else if (w_sdram_cs)
         cpu_data_out = w_sdram_data_out;
     else
@@ -110,6 +115,16 @@ leds u_leds(
     .o_leds(leds)
 );
 
+timer u_timer(
+    .clk(clk_2),
+    .reset(~cpu_resb),
+    .i_data(cpu_data_in),
+    .o_data(w_timer_data_out),
+    .cs(w_timer_cs),
+    .rwb(cpu_rwb),
+    .addr(cpu_addr[2:0])
+);
+
 sdram_adapter u_sdram_adapter(
     .i_cpuclk(clk_2),
     .i_arst(~button_reset),

hw/efinix_fpga/super6502.xml

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<efx:project name="super6502" description="" last_change_date="Thu December 29 2022 11:13:49" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.1.226" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="new" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project name="super6502" description="" last_change_date="Thu December 29 2022 11:49:30" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.1.226" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion"/>
         <efx:device name="T20F256"/>

hw/efinix_fpga/test_programs/Makefile

@@ -1,4 +1,4 @@
-TARGETS=stacktest runram
+TARGETS=stacktest runram timer
 
 all: $(TARGETS)
 
@@ -7,6 +7,6 @@ $(TARGETS):
 	xxd -ps $@ | fold -w 2 > $@.hex
 
 clean:
-	rm $(TARGETS)
+	rm -f $(TARGETS)
 	rm *.hex
 	rm *.list

hw/efinix_fpga/test_programs/timer.s

@@ -0,0 +1,38 @@
+.code
+
+LEDS = $efff
+TIMER_BASE = $eff8
+TIMER_DIVISOR = 5
+
+TIMER_OLD = $10
+
+main:
+    lda #$ff
+    sta TIMER_BASE+TIMER_DIVISOR
+    lda TIMER_BASE
+    sta TIMER_OLD
+    stz LEDS
+
+
+; load the new value of the timer in a
+; subtract the old value of the timer
+; if the result is greater than 30, then do something
+
+loop:
+    lda TIMER_BASE
+    tax
+    sec
+    sbc TIMER_OLD
+    sec
+    sbc #$20
+    bcc loop
+
+    stx TIMER_OLD
+    inc LEDS
+    bra loop
+    
+.segment "VECTORS"
+
+.addr main
+.addr main
+.addr main

hw/efinix_fpga/timer.sv

@@ -22,13 +22,13 @@ logic [7:0] divisor, status, control;
 //  --------------------------------
 //  |   3   |   IRQ Counter High   |
 //  --------------------------------
-//  |   4   |       Reserved       |
+//  |   4   |       Control        |
 //  --------------------------------
 //  |   5   |       Divisor        |
 //  --------------------------------
 //  |   6   |       Status         |
 //  --------------------------------
-//  |   7   |       Control        |
+//  |   7   |       Reserved       |
 //  --------------------------------