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Merge branch '55-increase-sd-card-speed' into 'master'

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Resolve "Increase SD Card speed"

Closes #55

See merge request bslathi19/super6502!51
This commit is contained in:
Byron Lathi
2023-11-23 20:23:57 +00:00
parent 46f2b01446 8721c816fc
commit 8c6b262f0c
3 changed files with 49 additions and 27 deletions
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47
hw/efinix_fpga/src/spi_controller.sv
View File

@@ -1,5 +1,6 @@
module spi_controller(
input i_clk,
input i_clk_cpu,
input i_clk_50,
input i_rst,
input i_cs,
@@ -37,17 +38,16 @@ assign o_spi_cs = ~r_control[0];
assign o_spi_clk = spi_clk;
assign o_spi_mosi = r_spi_mosi;
always @(negedge i_clk) begin
logic working;
always @(negedge i_clk_cpu) begin
if (i_rst) begin
r_baud_rate <= 8'h1;
r_input_data <= '0;
r_output_data <= '0;
r_control <= '0;
r_clock_counter <= '0;
count <= '0;
spi_clk <= '0;
active <= '0;
end else begin
active <= '0;
if (~i_rwb & i_cs) begin
unique case (i_addr)
0: r_baud_rate <= i_data;
@@ -59,28 +59,49 @@ always @(negedge i_clk) begin
3: r_control <= i_data;
endcase
end
working <= active_f;
end
if (active) begin
r_spi_mosi <= r_output_data[7];
end
logic active_f;
logic [7:0] r_output_data_f;
logic reset_f;
always @(posedge i_clk_50) begin
reset_f <= i_rst;
end
always @(posedge i_clk_50) begin
if (reset_f) begin
r_input_data <= '0;
r_clock_counter <= '0;
count <= '0;
spi_clk <= '0;
end
if (active_f) begin
r_spi_mosi <= r_output_data_f[7];
r_clock_counter <= r_clock_counter + 9'b1;
if (r_clock_counter >= r_baud_rate) begin
r_clock_counter <= '0;
spi_clk <= ~spi_clk;
// rising edge
if (spi_clk == '0) begin
r_output_data <= r_output_data << 1;
r_output_data_f <= r_output_data_f << 1;
count <= count + 1;
end
// falling edge
if (spi_clk == '1) begin
r_input_data <= {r_input_data[6:0], i_spi_miso};
if (count == '0) begin
active <= '0;
active_f <= '0;
end
end
end
end
end else begin
r_output_data_f <= r_output_data;
active_f <= active;
end
end
@@ -89,7 +110,7 @@ always_comb begin
0: o_data = r_baud_rate;
1: o_data = r_input_data;
2:;
3: o_data = {active, r_control[6:0]};
3: o_data = {working, r_control[6:0]};
default: o_data = 'x;
endcase
end

3
hw/efinix_fpga/src/super6502.sv
View File

@@ -250,7 +250,8 @@ uart_wrapper u_uart(
assign w_int_in[1] = w_uart_irq;
spi_controller spi_controller(
.i_clk(clk_cpu),
.i_clk_cpu(clk_cpu),
.i_clk_50(clk_50),
.i_rst(~cpu_resb),
.i_cs(w_spi_cs),
.i_rwb(cpu_rwb),

2
hw/efinix_fpga/super6502.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Sun November 19 2023 15:04:04" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project name="super6502" description="" last_change_date="Thu November 23 2023 12:03:00" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>