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Add verilog ethernet

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Byron Lathi
2024-08-19 17:40:05 -07:00
parent b521bbe5cf
commit 8e87345f22
2 changed files with 4 additions and 0 deletions
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3
.gitmodules vendored
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@@ -13,3 +13,6 @@
[submodule "hw/super6502_fpga/src/sub/sdspi"] [submodule "hw/super6502_fpga/src/sub/sdspi"]
path = hw/super6502_fpga/src/sub/sd_controller_wrapper/sdspi path = hw/super6502_fpga/src/sub/sd_controller_wrapper/sdspi
url = ../sdspi.git url = ../sdspi.git
[submodule "hw/super6502_fpga/src/sub/verilog-ethernet"]
path = hw/super6502_fpga/src/sub/verilog-ethernet
url = ../verilog-ethernet.git

1
hw/super6502_fpga/src/sub/verilog-ethernet Submodule

Submodule hw/super6502_fpga/src/sub/verilog-ethernet added at 2542187ec9