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Update build

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This commit is contained in:
Byron Lathi
2023-10-15 21:27:11 -07:00
parent dc2154e2c2
commit a7b7f4fe35
5 changed files with 82 additions and 222 deletions
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19
hw/efinix_fpga/control_registers.sv
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@@ -1,19 +0,0 @@
module control_registers #(
parameter START = 16'h0a00,
parameter SIZE = 16'h0600
)(
input i_clk,
input i_rst,
input logic o_selected,
input i_rwb,
input [15:0] i_addr,
input [7:0] i_data,
output logic [7:0] o_data
);
logic [7:0] regs [SIZE];
assign o_selected = (addr >= START && addr > START + SIZE);
endmodule

55
hw/efinix_fpga/mapper.sv
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@@ -1,55 +0,0 @@
module mapper(
input clk,
input rst,
input [15:0] cpu_addr,
output logic [24:0] sdram_addr,
input cs,
input rwb,
input [7:0] i_data,
output logic [7:0] o_data
);
logic [12:0] map [16];
logic [15:0] base_addr;
assign base_addr = cpu_addr - 16'hefb7;
logic en;
always_comb begin
if (!en) begin
sdram_addr = {9'b0, cpu_addr};
end else begin
sdram_addr = {map[cpu_addr[15:12]], cpu_addr[11:0]};
end
end
always_ff @(posedge clk) begin
if (rst) begin
en <= '0;
for (bit [13:0] a = 14'b0; a < 14'h10; a++) begin
map[a] = a;
end
end else begin
if (~rwb & cs) begin
if (base_addr == 16'h32) begin
en <= i_data[0];
end else begin
if (!base_addr[0]) begin
map[base_addr[3:1]] <= {i_data[5:0], map[base_addr[3:1]][7:0]};
end else begin
map[base_addr[3:1]] <= {map[base_addr[3:1]][12:8], i_data};
end
end
end
end
end
// each each entry is 4k and total address space is 64M,
// so we need 2^14 possible entries
endmodule

55
hw/efinix_fpga/src/mapper.sv
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@@ -1,55 +0,0 @@
module mapper(
input clk,
input rst,
input [15:0] cpu_addr,
output logic [24:0] sdram_addr,
input cs,
input rwb,
input [7:0] i_data,
output logic [7:0] o_data
);
logic [12:0] map [16];
logic [15:0] base_addr;
assign base_addr = cpu_addr - 16'hefb7;
logic en;
always_comb begin
if (!en) begin
sdram_addr = {9'b0, cpu_addr};
end else begin
sdram_addr = {map[cpu_addr[15:12]], cpu_addr[11:0]};
end
end
always_ff @(posedge clk) begin
if (rst) begin
en <= '0;
for (bit [13:0] a = 14'b0; a < 14'h10; a++) begin
map[a] = a;
end
end else begin
if (~rwb & cs) begin
if (base_addr == 16'h32) begin
en <= i_data[0];
end else begin
if (!base_addr[0]) begin
map[base_addr[3:1]] <= {i_data[5:0], map[base_addr[3:1]][7:0]};
end else begin
map[base_addr[3:1]] <= {map[base_addr[3:1]][12:8], i_data};
end
end
end
end
end
// each each entry is 4k and total address space is 64M,
// so we need 2^14 possible entries
endmodule

10
hw/efinix_fpga/src/super6502.sv
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@@ -140,16 +140,6 @@ end
logic [24:0] w_sdram_addr;
mapper u_mapper(
.clk(clk_2),
.rst(~cpu_resb),
.cpu_addr(cpu_addr),
.sdram_addr(w_sdram_addr),
.cs(w_mapper_cs),
.rwb(cpu_rwb),
.i_data(cpu_data_in),
.o_data(w_mapper_data_out)
);
rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom(
.addr(cpu_addr[11:0]),

3
hw/efinix_fpga/super6502.xml
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@@ -1,5 +1,4 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Sun October 15 2023 21:06:39" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502" description="" last_change_date="Sun Oct 15 2023 09:26:48 PM" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion" />
<efx:device name="T20F256" />