Build software correctly, ignore debugger files

.gitignore

@@ -1,4 +1,22 @@
 .vscode
 .~lock*
 
-.user_venv/
+.user_venv/
+
+
+# Software build files
+*.map
+*.list
+*.bin
+*.o
+
+
+# Efinix Debugger
+*.log*
+*.vcd
+*.gtkw
+*debug_profile*
+
+
+*.mem
+

Makefile

@@ -21,12 +21,13 @@ $(INIT_HEX): toolchain script/generate_rom_image.py $(HEX)
 	python script/generate_rom_image.py -i $(HEX) -o $@
 
 $(HEX):
-	$(MAKE) -C sw/$(ROM) $(notdir $@)
+	$(MAKE) -C sw/$(ROM_TARGET) $(notdir $@)
 
 .PHONY: clean
 clean:
 	$(MAKE) -C hw/super6502_fpga $@
+	$(MAKE) -C sw/$(ROM_TARGET) clean
 
 .PHONY: distclean
 distclean: clean
-	$(MAKE) -C sw/toolchain/cc65 clean
+	$(MAKE) -C sw/toolchain/cc65 clean

hw/super6502_fpga/init_hex.mem

@@ -1,65 +0,0 @@
-@00000000
-8d00a9
-200cd02
-801a03d0
-fe80f5
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-ff000000
-ff00ff00

hw/super6502_fpga/super6502_fpga.xml

@@ -1,4 +1,4 @@
-<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Sun Mar 03 2024 12:51:24 PM" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Sun Mar 03 2024 14:48:43" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion" />
         <efx:device name="T20F256" />
@@ -81,9 +81,4 @@
         <efx:param name="cold_boot" value="off" value_type="e_bool" />
         <efx:param name="cascade" value="off" value_type="e_option" />
     </efx:bitstream_generation>
-    <efx:debugger>
-        <efx:param name="work_dir" value="work_dbg" value_type="e_string" />
-        <efx:param name="auto_instantiation" value="off" value_type="e_bool" />
-        <efx:param name="profile" value="NONE" value_type="e_string" />
-    </efx:debugger>
 </efx:project>

sw/test_code/loop_test/lists/main.s.list

@@ -1,31 +0,0 @@
-ca65 V2.19 - Git 71b58f796
-Main file   : main.s
-Current file: main.s
-
-000000r 1               .export _init, _nmi_int, _irq_int
-000000r 1               
-000000r 1               
-000000r 1               SDRAM = $200
-000000r 1               
-000000r 1               .segment  "VECTORS"
-000000r 1               
-000000r 1  rr rr        .addr      _nmi_int    ; NMI vector
-000002r 1  rr rr        .addr      _init       ; Reset vector
-000004r 1  rr rr        .addr      _irq_int    ; IRQ/BRK vector
-000006r 1               
-000006r 1               .code
-000000r 1               
-000000r 1               _nmi_int:
-000000r 1               _irq_int:
-000000r 1               
-000000r 1               _init:
-000000r 1  A9 00                lda #$00
-000002r 1               @start:
-000002r 1  8D 00 02             sta SDRAM
-000005r 1  CD 00 02             cmp SDRAM
-000008r 1  D0 03                bne @end
-00000Ar 1  1A                   ina
-00000Br 1  80 F5                bra @start
-00000Dr 1               
-00000Dr 1  80 FE        @end:   bra @end
-00000Dr 1               

sw/test_code/loop_test/loop_test.map

@@ -1,28 +0,0 @@
-Modules list:
--------------
-main.o:
-    CODE              Offs=000000  Size=00000F  Align=00001  Fill=0000
-    VECTORS           Offs=000000  Size=000006  Align=00001  Fill=0000
-
-
-Segment list:
--------------
-Name                   Start     End    Size  Align
-----------------------------------------------------
-CODE                  00FF00  00FF0E  00000F  00001
-VECTORS               00FFFA  00FFFF  000006  00001
-
-
-Exports list by name:
----------------------
-
-
-
-Exports list by value:
-----------------------
-
-
-
-Imports list:
--------------
-